公开(公告)号：US20240347081A1

公开(公告)日：2024-10-17

申请号：US18633362

申请日：2024-04-11

Applicant: Micron Technology, Inc.

Inventor： Hernan A. Castro ,  Mattia Boniardi ,  Innocenzo Tortorelli

IPC: G11C7/10 ,  G11C16/34

CPC classification number: G11C7/1039 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093 ,  G11C16/3404

Abstract: Methods, systems, and devices for pulse based multi-level cell programming are described. A memory device may identify an intermediate logic state to store to a multi-level memory cell capable of storing three or more logic states. The memory device may apply a first pulse with a first polarity to the memory cell to store a SET or RESET state to the memory cell based on identifying the intermediate logic state. As such, the memory device may identify a threshold voltage of the memory cell that stores the SET or RESET state. The memory device may apply a quantity of pulses to the memory cell to store the identified intermediate logic state based on identifying the threshold voltage of the memory cell that stores the SET or RESET state. In some examples, the quantity of pulses may have a second polarity different than the first polarity.

公开(公告)号：US12119055B2

公开(公告)日：2024-10-15

申请号：US17329028

申请日：2021-05-24

Applicant: Micron Technology, Inc.

Inventor： Hernan A. Castro ,  Everardo Torres Flores ,  Jeremy M. Hirst

IPC: G11C13/00 ,  G11C5/02 ,  G11C5/06 ,  H10B63/00 ,  G11C8/08 ,  H10N70/00 ,  H10N70/20

CPC classification number: G11C13/0004 ,  G11C5/025 ,  G11C5/063 ,  G11C13/0023 ,  H10B63/24 ,  H10B63/30 ,  H10B63/80 ,  H10B63/84 ,  G11C8/08 ,  G11C2213/71 ,  G11C2213/77 ,  H10N70/231 ,  H10N70/826 ,  H10N70/8828

Abstract: Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.

公开(公告)号：US20240312534A1

公开(公告)日：2024-09-19

申请号：US18669140

申请日：2024-05-20

Applicant: Micron Technology, Inc.

Inventor： Jeremy M. Hirst ,  Shanky K. Jain ,  Hernan A. Castro ,  Richard K. Dodge ,  William A. Melton

IPC: G11C16/34 ,  G06F16/21 ,  G06F16/587 ,  G11C11/56 ,  G11C13/00 ,  G11C16/12 ,  G11C16/26

CPC classification number: G11C16/34 ,  G06F16/219 ,  G06F16/587 ,  G11C11/5614 ,  G11C13/0004 ,  G11C13/0069 ,  G11C16/12 ,  G11C16/26 ,  G11C2213/77

Abstract: The present disclosure includes apparatuses, methods, and systems for multi-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of a plurality of possible data states by applying a voltage pulse to the memory cell, determining the memory cell snaps back in response to the applied voltage pulse, turning off a current to the memory cell upon determining the memory cell snaps back, and applying a number of additional voltage pulses to the memory cell after turning off the current to the memory cell.

公开(公告)号：US20240120006A1

公开(公告)日：2024-04-11

申请号：US18545245

申请日：2023-12-19

Applicant: Micron Technology, Inc.

Inventor： Hernan A. Castro ,  Jeremy M. Hirst ,  Shanky K. Jain ,  Richard K. Dodge ,  William A. Melton

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/003 ,  G11C13/004 ,  G11C2013/0078 ,  G11C2213/15 ,  G11C2213/71

Abstract: The present disclosure includes apparatuses, methods, and systems for three-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of three possible data states by applying a voltage pulse to the memory cell, determining whether the memory cell snaps back in response to the applied voltage pulse, and applying an additional voltage pulse to the memory cell based on the determination of whether the memory cell snaps back.

公开(公告)号：US11915124B2

公开(公告)日：2024-02-27

申请号：US16887665

申请日：2020-05-29

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Hernan A. Castro ,  Ameen D. Akel

IPC: G06N3/063 ,  G06F12/06 ,  G06N3/04

CPC classification number: G06N3/063 ,  G06F12/0646 ,  G06N3/04 ,  G06F2212/1008

Abstract: Methods, apparatuses, and systems for in- or near-memory processing are described. Spiking events in a spiking neural network may be processed via a memory system. A memory system may store a group of destination neurons, and at each time interval in a series of time intervals of a spiking neural network (SNN), pass through a group of pre-synaptic spike events from respective source neurons, wherein the group of pre-synaptic spike events are subsequently stored in memory.

公开(公告)号：US11653505B2

公开(公告)日：2023-05-16

申请号：US17174027

申请日：2021-02-11

Applicant: Micron Technology, Inc.

Inventor： Hernan A. Castro ,  Stephen H. Tang ,  Stephen W. Russell

IPC: H01L27/24 ,  H01L27/11514 ,  H01L45/00 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L27/249 ,  H01L27/11514 ,  H01L21/76816 ,  H01L23/5226 ,  H01L45/065 ,  H01L45/085 ,  H01L45/16 ,  H01L45/1683

Abstract: Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.

公开(公告)号：US20230126926A1

公开(公告)日：2023-04-27

申请号：US17950895

申请日：2022-09-22

Applicant: Micron Technology, Inc.

Inventor： Hernan A. Castro

IPC: G11C8/12 ,  H03K19/1776 ,  G11C5/02 ,  G11C8/10

Abstract: Methods, systems, and devices for edgeless memory clusters are described. Systems, devices, and techniques are described for eliminating gaps between clusters by creating groups (e.g., domains) of clusters that are active at a given time, and using drivers within inactive clusters to perform array termination functions for abutting active clusters. Tiles on the edges of a cluster may have drivers that operate both for the cluster, and for a neighboring cluster, with circuits (e.g., a multiplexers) on the drivers to enable operations for both clusters.

公开(公告)号：US11522014B2

公开(公告)日：2022-12-06

申请号：US16871957

申请日：2020-05-11

Applicant: Micron Technology, Inc.

Inventor： Hernan A. Castro

IPC: H01L27/24 ,  G11C13/00 ,  H01L45/00 ,  G11C7/18 ,  G11C8/14

Abstract: Subject matter disclosed herein relates to an integrated circuit device having a socket interconnect region for connecting a plurality of conductive lines at a first vertical level to interconnect structures formed at a second vertical level different from the first vertical level. The conductive lines include a plurality of contacted lines that are vertically connected to the interconnect structures at the socket interconnect region, a plurality of terminating lines terminating at the socket interconnect region, and a plurality of pass-through lines that pass through the socket interconnect region without being vertically connected and without being terminated at the socket interconnect region.

公开(公告)号：US11430511B2

公开(公告)日：2022-08-30

申请号：US17118102

申请日：2020-12-10

Applicant: Micron Technology, Inc.

Inventor： Hernan A. Castro

IPC: G11C13/00 ,  G11C11/56 ,  G11C15/04

Abstract: In an example, a method may include comparing input data to stored data stored in a memory cell and determining whether the input data matches the stored data based on whether the memory cell snaps back in response to an applied voltage differential across the memory cell.

公开(公告)号：US11302393B2

公开(公告)日：2022-04-12

申请号：US17024248

申请日：2020-09-17

Applicant: Micron Technology, Inc.

Inventor： Hernan A. Castro ,  Innocenzo Tortorelli ,  Agostino Pirovano ,  Fabio Pellizzer

IPC: G11C13/00 ,  G11C5/06

Abstract: Techniques are provided for programming a self-selecting memory cell that stores a first logic state. To program the memory cell, a pulse having a first polarity may be applied to the cell, which may result in the memory cell having a reduced threshold voltage. During a duration in which the threshold voltage of the memory cell may be reduced (e.g., during a selection time), a second pulse having a second polarity (e.g., a different polarity) may be applied to the memory cell. Applying the second pulse to the memory cell may result in the memory cell storing a second logic state different than the first logic state.