公开(公告)号：US06849387B2

公开(公告)日：2005-02-01

申请号：US10081479

申请日：2002-02-21

申请人： Min-Hsiung Chiang ,  Chi-Hsin Lo

发明人： Min-Hsiung Chiang ,  Chi-Hsin Lo

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/532 ,  H01L21/8238

CPC分类号： H01L23/5223 ,  H01L21/76808 ,  H01L21/76838 ,  H01L23/53238 ,  H01L27/10852 ,  H01L27/10882 ,  H01L27/10894 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for integrating copper with an MIM capacitor during the formation the MIM capacitor. The MIM capacitor is generally formed upon a substrate and at least one copper layer is deposited upon the substrate and layers thereof to form at least one metal layer from which the MIM capacitor is formed, such that the MIM capacitor may be adapted for use with an embedded DRAM device. The MIM capacitor comprises a low-temperature MIM capacitor. At least one DRAM crown photo layer may be formed upon the substrate and layers thereof to form the MIM capacitor. The number of additional lithographic steps required in BEOL manufacturing operations is thus only one, while the capacitance of the MIM capacitor can be improved greatly because the sequential process of the DRAM crown photo patterning steps may be altered.

摘要翻译： 在MIM电容器形成期间，将铜与MIM电容器集成的方法。 MIM电容器通常形成在衬底上，并且至少一个铜层沉积在衬底及其层上以形成MIM电容器形成的至少一个金属层，使得MIM电容器可适用于 嵌入式DRAM设备。 MIM电容器包括低温MIM电容器。 可以在衬底及其层上形成至少一个DRAM冠光敏层以形成MIM电容器。 因此，在BEOL制造操作中所需的附加光刻步骤的数量仅为一个，而MIM电容器的电容可以大大提高，因为可以改变DRAM冠光栅图案化步骤的顺序处理。

公开(公告)号：US06600228B2

公开(公告)日：2003-07-29

申请号：US09929676

申请日：2001-08-15

申请人： Yu-Hua Lee ,  Min-Hsiung Chiang ,  Jenn Ming Huang

发明人： Yu-Hua Lee ,  Min-Hsiung Chiang ,  Jenn Ming Huang

IPC分类号： H01L214763

CPC分类号： H01L23/3192 ,  H01L2924/0002 ,  H01L2924/00

摘要： A planarized surface of a photoresist layer is formed above a layer formed over a hole in a blanket, conformal, silicon nitride layer which in turn is formed above a keyhole in metallization with SOG layers therebetween on the surface of a semiconductor device. A blanket, first photoresist layer was formed above the blanket silicon nitride to fill the damage to the surface caused by the hole. Then the first photoresist layer was stripped leaving a residual portion of the first photoresist layer filling the hole. Next, a blanket, second photoresist layer was formed above the blanket layer. The hole has a neck with a width from about 200 Å to about 500 Å and the hole has a deep, pocket-like gap with a cross-section with a width from about 500 Å to about 1200 Å below the narrow neck.

摘要翻译： 光致抗蚀剂层的平坦化表面形成在形成在覆盖层中的孔的上方的层上，保形的氮化硅层，其又形成在半导体器件的表面上的SOG层之间的金属化中的锁孔上方。 在覆盖氮化硅上方形成毯状的第一光致抗蚀剂层，以填充由孔引起的对表面的损伤。 然后剥离第一光致抗蚀剂层，留下填充孔的第一光致抗蚀剂层的残留部分。 接下来，在覆盖层上方形成毯状的第二光致抗蚀剂层。 该孔具有宽度从大约至大约500埃的颈部，并且该孔具有深的袋状间隙，其横截面的宽度从窄到90度到大约在1200度。

公开(公告)号：US06383863B1

公开(公告)日：2002-05-07

申请号：US09963595

申请日：2001-09-27

申请人： Min-Hsiung Chiang ,  Hsiao-Hui Tseng ,  Hsien-Yuan Chang ,  Chung-Wei Chang ,  Kuo-Chyuan Tzeng

发明人： Min-Hsiung Chiang ,  Hsiao-Hui Tseng ,  Hsien-Yuan Chang ,  Chung-Wei Chang ,  Kuo-Chyuan Tzeng

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L21/76889 ,  H01L21/76897 ,  H01L27/10873 ,  H01L27/10888 ,  H01L28/84 ,  H01L28/90 ,  H01L29/66545

摘要： A process for integrating the formation of a salicide layer on DRAM word line structures, and on a bit line contact structure, has been developed. The process features selective etch back of the insulator layers embedding the tapered shaped bit line contact, and the tapered shape capacitor structures, exposing top surface portions of polysilicon word line structures. The selective etch back procedure also results in formation of insulator spacers on the sides of the tapered bit line contact, and capacitor structures, allowing a subsequent salicide procedure to form metal suicide layers only on the exposed top surfaces of the DRAM word line, bit line contact, and capacitor structures.

摘要翻译： 已经开发了一种用于将自对准硅化物层形成在DRAM字线结构上以及位线接触结构上的过程。 该工艺具有嵌入锥形位线接触件的绝缘体层的选择性回蚀和锥形形状电容器结构，暴露多晶硅字线结构的顶表面部分。 选择性回蚀程序还导致在锥形位线接触和电容器结构的侧面上形成绝缘体间隔物，并且允许随后的自对准硅化物程序仅在DRAM字线，位线的暴露的顶表面上形成金属硅化物层 接触和电容器结构。

公开(公告)号：US06020236A

公开(公告)日：2000-02-01

申请号：US257723

申请日：1999-02-25

申请人： Yu-Hua Lee ,  James Wu ,  Wen-Chuan Chiang ,  Min-Hsiung Chiang

发明人： Yu-Hua Lee ,  James Wu ,  Wen-Chuan Chiang ,  Min-Hsiung Chiang

IPC分类号： H01L21/8242

CPC分类号： H01L27/10852

摘要： A method to form capacitance node contacts with improved isolation in a DRAM process is described. An isolation layer is formed on a semiconductor substrate. A first contact hole is formed and filled with a polysilicon plug and the top surface of the isolation layer and of the polysilicon plug are polished to a planar surface. A first interpoly isolation layer is deposited. A stopping layer is deposited. A capping layer is deposited. A first polysilicon layer is deposited. The first polysilicon layer is etched to form features. A second interpoly isolation layer is deposited. The second interpoly isolation layer is planarized. The second contact hole is etched through the second interpoly isolation layer and the capping layer. The exposed first polysilicon material is etched back to the vertical sides of the second contact hole. The stopping layer and the first interpoly isolation layer are etched through to the top surface of the polysilicon plug. A lining layer of silicon nitride is deposited and etched to remain only on the vertical interior surfaces of the second contact hole. A second polysilicon layer is deposited to fill the second contact hole. The second polysilicon layer and the second interpoly isolation layer are planarized. The fabrication of the integrated circuit device is completed.

摘要翻译： 描述了在DRAM处理中形成具有改进的隔离的电容节点触点的方法。 在半导体衬底上形成隔离层。 形成第一接触孔并填充多晶硅插塞，并且隔离层和多晶硅插塞的顶表面被抛光到平坦表面。 沉积第一间隔隔离层。 沉积停止层。 沉积覆盖层。 沉积第一多晶硅层。 第一多晶硅层被蚀刻以形成特征。 沉积第二个互隔离层。 第二间隔隔离层被平坦化。 第二接触孔被蚀刻穿过第二多晶硅隔离层和封盖层。 暴露的第一多晶硅材料被回蚀刻到第二接触孔的垂直侧。 停止层和第一互隔离层被蚀刻到多晶硅插塞的顶表面。 沉积和蚀刻氮化硅的内衬层以仅保留在第二接触孔的垂直内表面上。 沉积第二多晶硅层以填充第二接触孔。 第二多晶硅层和第二多晶硅隔离层被平坦化。 完成集成电路器件的制造。

公开(公告)号：US07208369B2

公开(公告)日：2007-04-24

申请号：US10662609

申请日：2003-09-15

申请人： Chih-Yang Pai ,  Min-Hsiung Chiang ,  Chen-Jong Wang ,  Shou-Gwo Wuu

发明人： Chih-Yang Pai ,  Min-Hsiung Chiang ,  Chen-Jong Wang ,  Shou-Gwo Wuu

IPC分类号： H01L21/8242

CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1116 ,  H01L28/40 ,  Y10S257/903 ,  Y10S257/904

摘要： Semiconductor devices having a dual polysilicon electrode and a method of manufacturing are provided. The semiconductor devices include a first polysilicon layer deposited on a second polysilicon layer. Each polysilicon layer may be doped individually. The method also allows for some semiconductor devices on a wafer to have a single polysilicon wafer and other devices to have a dual polysilicon layer. In one embodiment, the semiconductor devices are utilized to form a memory device wherein the storage capacitors and transistors located in the cell region are formed with a dual polysilicon layer and devices in the periphery region are formed with a single polysilicon layer.

摘要翻译： 提供了具有双重多晶硅电极的半导体器件和制造方法。 半导体器件包括沉积在第二多晶硅层上的第一多晶硅层。 每个多晶硅层可以单独掺杂。 该方法还允许晶片上的一些半导体器件具有单个多晶硅晶片和其它器件以具有双重多晶硅层。 在一个实施例中，半导体器件用于形成存储器件，其中位于单元区域中的存储电容器和晶体管形成双重多晶硅层，并且外围区域中的器件形成有单个多晶硅层。

公开(公告)号：US20050112876A1

公开(公告)日：2005-05-26

申请号：US10723237

申请日：2003-11-26

申请人： Chih-Ta Wu ,  Kuo Yin Lin ,  Min-Hsiung Chiang

发明人： Chih-Ta Wu ,  Kuo Yin Lin ,  Min-Hsiung Chiang

IPC分类号： C23C16/34 ,  C23C16/56 ,  H01L21/20 ,  H01L21/768

CPC分类号： C23C16/56 ,  C23C16/34 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76862

摘要： A method is described for a plasma treatment of a TiCl4 based CVD deposited TiN layer that reduces stress, lowers resistivity, and improves film stability. Resistivity is stable in an air ambient for up to 48 hours after the plasma treatment. A TiN layer is treated with a N-containing plasma that includes N2, NH3, or N2H4 at a temperature between 500° C. and 700° C. Optionally, H2 may be added to N2 in the plasma step which removes chloride impurities and densifies the TiN layer. The TiN layer may serve as a barrier layer, an ARC layer, or as a bottom electrode in a MIM capacitor. An improved resistance of the treated TiN layer to oxidation during formation of an oxide based insulator layer and a lower leakage current in the MIM capacitor is also achieved.

摘要翻译： 描述了一种用于等离子体处理基于TiCl 4的CVD沉积TiN层的方法，其降低应力，降低电阻率并提高膜的稳定性。 等离子体处理后电阻率在空气环境中稳定长达48小时。 用含N的等离子体处理TiN层，该等离子体包括N 2，NH 3或N 2 H 4， 在500℃至700℃之间的温度下，可以在等离子体步骤中将H 2 N加入到N 2 N中，除去氯化物杂质并致密化 TiN层。 TiN层可以用作MIM电容器中的阻挡层，ARC层或底电极。 还实现了在形成氧化物基绝缘体层期间处理的TiN层对氧化的改善的电阻和MIM电容器中较低的漏电流。

公开(公告)号：US06294456B1

公开(公告)日：2001-09-25

申请号：US09200589

申请日：1998-11-27

申请人： Yu-Hua Lee ,  Min-Hsiung Chiang ,  Jenn Ming Huang

发明人： Yu-Hua Lee ,  Min-Hsiung Chiang ,  Jenn Ming Huang

IPC分类号： H01L214763

CPC分类号： H01L23/3192 ,  H01L2924/0002 ,  H01L2924/00

摘要： This is a method of planarizing a surface of a photoresist layer formed above a layer formed over a gap in a blanket silicon nitride layer which in turn is formed above a keyhole in metallization with SOG layers therebetween on the surface of a semiconductor device. The following steps are performed. Form a blanket, first photoresist layer above the blanket silicon nitride with a damaged surface caused by the gap. Then strip the first photoresist layer leaving a residual portion of the first photoresist layer in the gap. Next, form a blanket, second photoresist layer above the blanket layer. The gap has a neck with a width from about 200 Å to about 500 Å and the gap has a deep, pocket-like cross-section with a width from about 500 Å to about 1,200 Å below the narrow neck. Partial stripping of the first photoresist layer, which follows, is performed by an etching process including wet and dry processing.

摘要翻译： 这是在形成在覆盖氮化硅层的间隙上形成的层上形成的光致抗蚀剂层的表面的平面化方法，该覆盖氮化硅层又在半导体器件的表面上的SOG层之间的金属化形成在键孔上方。 执行以下步骤。 在覆盖氮化硅之上形成一个毯子，第一个光刻胶层，由间隙引起损坏的表面。 然后剥离第一光致抗蚀剂层，留下间隙中的第一光致抗蚀剂层的残留部分。 接下来，在覆盖层上方形成毯状的第二光致抗蚀剂层。 间隙具有宽度从大约至大约500埃的颈部，并且间隙具有深的袋状横截面，宽度在窄的颈部以下从大约500到大约1,200埃。 通过包括湿法和干法处理的蚀刻工艺进行随后的第一光致抗蚀剂层的部分剥离。

公开(公告)号：US6100116A

公开(公告)日：2000-08-08

申请号：US99144

申请日：1998-06-18

申请人： Yu-Hua Lee ,  James Wu ,  Jenn Ming Huang ,  Cheng-Yeh Shih ,  Min-Hsiung Chiang

发明人： Yu-Hua Lee ,  James Wu ,  Jenn Ming Huang ,  Cheng-Yeh Shih ,  Min-Hsiung Chiang

IPC分类号： H01L23/525 ,  H01L21/82

CPC分类号： H01L23/5258 ,  H01L2924/0002

摘要： A method for forming protection layers completely around a metal fuse to protect the metal fuse 74A and metal lines 74B from moisture corrosion from fuse opening and micro-cracks in dielectric layers. The invention surrounds the fuse on all sides with two protection layers: a bottom protection layer 70 and a top protection layer 78. The top protection layer 78 is formed over the fuse metal, the sidewalls of the metal fuse and the bottom protection layer 70. The protection layers 70 78 of the invention form a moisture proof seal structure around the metal fuse 74A and protect the metal fuse 74A and metal lines 74B from moisture and contaminates.

摘要翻译： 一种用于在金属保险丝周围完全形成保护层的方法，用于保护金属保险丝74A和金属线74B免受保险丝开口的湿度腐蚀和电介质层中的微裂纹。 本发明在所有侧面上具有两个保护层的保险丝：底部保护层70和顶部保护层78.顶部保护层78形成在熔丝金属，金属熔断器的侧壁和底部保护层70上。 本发明的保护层70 78在金属熔断器74A周围形成防潮密封结构，并且保护金属熔断器74A和金属线74B免受潮湿和污染。

公开(公告)号：US07180116B2

公开(公告)日：2007-02-20

申请号：US10861148

申请日：2004-06-04

申请人： Min-Hsiung Chiang ,  Chih-Ta Wu ,  Tsung-Hsun Huang

发明人： Min-Hsiung Chiang ,  Chih-Ta Wu ,  Tsung-Hsun Huang

IPC分类号： H01L27/108

CPC分类号： H01L27/0629 ,  H01L27/1085 ,  H01L27/10867 ,  H01L29/6659

摘要： A method of forming a capacitor comprising the following steps. An inchoate capacitor is formed on a substrate within a capacitor area whereby portions of the substrate separate the inchoate capacitor from isolating shallow trench isolation (STI) structures. STIs. A first dielectric layer is formed over the structure. The first dielectric layer is patterned to: form a portion masking the inchoate capacitor; and expose at least portions of the STIs and the substrate portions separating the inchoate capacitor from the shallow trench isolation structures. Metal portions are formed at least over the substrate portions. A second dielectric layer is formed over the patterned first dielectric layer portion, the metal portions and the STIs, whereby the metal portions formed at least over the substrate portions prevent formation of native oxide on at least the substrate portions. The invention also includes the structures formed thereby.

摘要翻译： 一种形成电容器的方法，包括以下步骤。 在电容器区域中的衬底上形成初始电容器，由此衬底的一部分使得初始电容器与隔离浅沟槽隔离（STI）结构分离。 性传播感染 在结构上形成第一介电层。 将第一电介质层图案化为：形成遮蔽复合电容器的部分; 并且暴露STI和至少部分将初步电容器与浅沟槽隔离结构分开的衬底部分。 金属部分至少形成在衬底部分上。 在图案化的第一介电层部分，金属部分和STI上形成第二电介质层，由此至少在衬底部分上形成的金属部分防止在至少衬底部分上形成自然氧化物。 本发明还包括由此形成的结构。

公开(公告)号：US20060057803A1

公开(公告)日：2006-03-16

申请号：US11264447

申请日：2005-11-01

申请人： Min-Hsiung Chiang

发明人： Min-Hsiung Chiang

IPC分类号： H01L21/8242 ,  H01L21/20

CPC分类号： H01L27/1087 ,  H01L27/10894

摘要： A method of integrating the fabrication of a capacitor cell and a logic device region, wherein the surface area of a capacitor region is increased, and the risk of a capacitor depletion phenomena is reduced, has been developed. After formation of insulator filled STI regions featuring tapered sides, a portion of the insulator layer in an STI region is recessed below the top surface of the semiconductor substrate exposing a bare, tapered side of the semiconductor substrate. Ion implantation into the tapered side of the portion of semiconductor substrate exposed in the recessed STI portion, as well as into a top portion of semiconductor substrate located adjacent to the recessed STI portion, results in formation of a capacitor region now greater in surface area than a counterpart capacitor region which is formed via implantation into only a top portion of semiconductor substrate. Growth of a gate insulator layer and definition of gate structures in the logic device region, also simultaneously forms a capacitor dielectric layer on the underlying capacitor region, as well as a capacitor plate structure in the capacitor cell region.

摘要翻译： 已经开发了集成电容器单元和逻辑器件区域的制造的方法，其中电容器区域的表面积增加，并且电容器耗尽现象的风险降低。 在形成具有锥形侧面的绝缘体填充的STI区域之后，STI区域中的绝缘体层的一部分在半导体衬底的顶表面下方露出，露出半导体衬底的裸露的锥形侧。 离子注入到暴露在凹陷STI部分中的半导体衬底的部分的锥形侧以及位于邻近凹陷STI部分的半导体衬底的顶部部分中，导致形成电容器区域现在表面积大于 通过仅注入半导体衬底的顶部形成的对应电容器区域。 栅极绝缘体层的生长和逻辑器件区域中栅极结构的定义也同时在下面的电容器区域上形成电容器电介质层，以及电容器单元区域中的电容器板结构。