公开(公告)号：US08451646B2

公开(公告)日：2013-05-28

申请号：US12854491

申请日：2010-08-11

申请人： Min-hwa Chi ,  Xiaohui Huang ,  Lijun Song ,  Jingang Wu ,  Deyuan Xiao

发明人： Min-hwa Chi ,  Xiaohui Huang ,  Lijun Song ,  Jingang Wu ,  Deyuan Xiao

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C13/003 ,  G11C2013/0071 ,  G11C2013/0078 ,  G11C2013/0083 ,  G11C2213/78 ,  G11C2213/79

摘要： A resistive random access memory utilizing gate induced drain leakage current as the read operation current and the write operation current and a method of operation the same, wherein the resistive random access memory including a plurality of arrayed memory cells, a plurality of bit-lines and a plurality word-lines, each memory cell including: a switching resistor having a first terminal and a second terminal, the first terminal of the switching resistor being connected to one bit-line; and a MOSFET being connected to the second terminal and having a gate, a source, a drain and a substrate, the gate being connected to one word-line, the read operation current and the write operation current of the memory cell being gate induced drain leakage current of the MOSFET. The RRAM array presented in this invention has superior scalability for resistors as well as transistors, which leads to a memory array with higher density.

摘要翻译： 一种利用栅极感应漏极漏电流作为读操作电流和写操作电流的电阻随机存取存储器及其操作方法，其中所述电阻随机存取存储器包括多个阵列存储单元，多个位线和 多个字线，每个存储单元包括：具有第一端子和第二端子的开关电阻器，所述开关电阻器的第一端子连接到一个位线; 以及连接到第二端子并且具有栅极，源极，漏极和衬底的MOSFET，栅极连接到一个字线，存储器单元的读取操作电流和写入操作电流是栅极感应漏极 MOSFET的漏电流。 在本发明中呈现的RRAM阵列对于电阻器和晶体管具有优异的可扩展性，这导致具有更高密度的存储器阵列。

公开(公告)号：US08264863B2

公开(公告)日：2012-09-11

申请号：US12869941

申请日：2010-08-27

申请人： Min-hwa Chi ,  Deyuan Xiao

发明人： Min-hwa Chi ,  Deyuan Xiao

IPC分类号： G11C11/22

CPC分类号： H01L27/1203 ,  B82Y10/00 ,  G11C11/22 ,  G11C11/223 ,  H01L21/28291 ,  H01L27/1159 ,  H01L29/6684 ,  H01L29/78391

摘要： The present disclosure provides a green transistor for nano-Si Ferro-electric random access memory (FeRAM) and method of operating the same. The nano-Si FeRAM includes a plurality of memory cells arranged in an array with bit-lines and word-lines, and each memory cell includes a MOSFET including a gate, a source, a drain, a substrate, and a data storage element formed on the drain spacer of the gate and made of nano-Si in porous SiO2; a word-line connected to the gate; a first bit-line connected to the drain; a second bit-line connected to the source; and an substrate bias supply connected to the substrate, and the gate induced drain leakage current of the MOSFET serves as the read current of the memory cell.

摘要翻译： 本公开提供了一种用于纳米Si铁电随机存取存储器（FeRAM）的绿色晶体管及其操作方法。 纳米SiFeRAM包括以位线和字线布置成阵列的多个存储单元，并且每个存储单元包括MOSFET，其包括栅极，源极，漏极，衬底和形成的数据存储元件 在栅极的漏极间隔，并由多孔SiO2中的纳米Si制成; 连接到门的字线; 连接到漏极的第一位线; 连接到源的第二位线; 以及连接到衬底的衬底偏置电源，并且MOSFET的栅极感应漏极漏电流用作存储器单元的读取电流。

公开(公告)号：US20110063888A1

公开(公告)日：2011-03-17

申请号：US12861622

申请日：2010-08-23

申请人： Min-hwa Chi ,  Deyuan Xiao

发明人： Min-hwa Chi ,  Deyuan Xiao

IPC分类号： G11C11/00 ,  H01L29/78

CPC分类号： G11C13/0007 ,  G11C11/5685 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/0475 ,  G11C2013/0054 ,  G11C2013/0073 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/2436

摘要： A random access memory includes a plurality of memory cells arrayed in bit-lines and word-lines. Each memory cell comprises a green transistor (gFET) including a gate, a source, and a drain; a switching resistor including a first terminal and a second terminal; and a reference resistor including a third terminal and a fourth terminal. The first terminal of the switching resistor and the third terminal is connected to a bit-line, the second terminal of the switching resistor is connected to the first source of the gFET, the fourth terminal of the reference resistor is connected to the second source of the gFET, and the gate of the gFET is connected to a word-line. The method of operating the RRAM includes a write operation and a read operation The write operation comprises steps of: applying a first voltage to the bit-line to perform a large voltage difference across the bit-line and the drain of the gFET, applying a second voltage to the gate of the gFET to turn on the gFET transiently, and a large current pulse flowing through the switching resistor for changing the resistance state. The read operation comprises steps of: applying a third voltage to the bit-line to perform a small voltage difference across the bit-line and the drain of the gFET, applying a second voltage to the word-line to turn on the gFET, and comparing the current through the switching resistor with the current through the reference resistor so as to read the data stored in the memory cell.

摘要翻译： 随机存取存储器包括以位线和字线排列的多个存储单元。 每个存储单元包括包括栅极，源极和漏极的绿色晶体管（gFET）; 开关电阻器，包括第一端子和第二端子; 以及包括第三端子和第四端子的参考电阻器。 开关电阻器和第三端子的第一端子连接到位线，开关电阻器的第二端子连接到gFET的第一源极，参考电阻器的第四端子连接到第二源极 gFET和gFET的栅极连接到字线。 操作RRAM的方法包括写入操作和读取操作。写入操作包括以下步骤：向位线施加第一电压以在gFET的位线和漏极之间执行大的电压差，施加 第二电压到gFET的栅极，瞬时导通gFET，并且大电流脉冲流过开关电阻器以改变电阻状态。 读取操作包括以下步骤：将第三电压施加到位线，以在gFET的位线和漏极之间执行小的电压差，向字线施加第二电压以导通gFET;以及 将通过开关电阻的电流与通过参考电阻的电流进行比较，以读取存储在存储单元中的数据。

公开(公告)号：US20110090731A1

公开(公告)日：2011-04-21

申请号：US12869941

申请日：2010-08-27

申请人： Min-hwa Chi ,  Deyuan Xiao

发明人： Min-hwa Chi ,  Deyuan Xiao

IPC分类号： G11C11/22 ,  H01L27/12

CPC分类号： H01L27/1203 ,  B82Y10/00 ,  G11C11/22 ,  G11C11/223 ,  H01L21/28291 ,  H01L27/1159 ,  H01L29/6684 ,  H01L29/78391

摘要： The present disclosure provides a green transistor for nano-Si Ferro-electric random access memory (FeRAM) and method of operating the same. The nano-Si FeRAM includes a plurality of memory cells arranged in an array with bit-lines and word-lines, and each memory cell includes a MOSFET including a gate, a source, a drain, a substrate, and a data storage element formed on the drain spacer of the gate and made of nano-Si in porous SiO2; a word-line connected to the gate; a first bit-line connected to the drain; a second bit-line connected to the source; and an substrate bias supply connected to the substrate, and the gate induced drain leakage current of the MOSFET serves as the read current of the memory cell.

摘要翻译： 本公开提供了一种用于纳米Si铁电随机存取存储器（FeRAM）的绿色晶体管及其操作方法。 纳米SiFeRAM包括以位线和字线布置成阵列的多个存储单元，并且每个存储单元包括MOSFET，其包括栅极，源极，漏极，衬底和形成的数据存储元件 在栅极的漏极间隔，并由多孔SiO2中的纳米Si制成; 连接到门的字线; 连接到漏极的第一位线; 连接到源的第二位线; 以及连接到衬底的衬底偏置电源，并且MOSFET的栅极感应漏极漏电流用作存储器单元的读取电流。

公开(公告)号：US08208286B2

公开(公告)日：2012-06-26

申请号：US12861622

申请日：2010-08-23

申请人： Min-Hwa Chi ,  Deyuan Xiao

发明人： Min-Hwa Chi ,  Deyuan Xiao

IPC分类号： G11C11/00 ,  G11C11/36 ,  H01L21/02

CPC分类号： G11C13/0007 ,  G11C11/5685 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/0475 ,  G11C2013/0054 ,  G11C2013/0073 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/2436

摘要： A random access memory includes a plurality of memory cells arrayed in bit-lines and word-lines. Each memory cell comprises a green transistor (gFET) including a gate, a source, and a drain; a switching resistor including a first terminal and a second terminal; and a reference resistor including a third terminal and a fourth terminal. The first terminal of the switching resistor and the third terminal is connected to a bit-line, the second terminal of the switching resistor is connected to the first source of the gFET, the fourth terminal of the reference resistor is connected to the second source of the gFET, and the gate of the gFET is connected to a word-line. The method of operating the RRAM includes a write operation and a read operation The write operation comprises steps of: applying a first voltage to the bit-line to perform a large voltage difference across the bit-line and the drain of the gFET, applying a second voltage to the gate of the gFET to turn on the gFET transiently, and a large current pulse flowing through the switching resistor for changing the resistance state. The read operation comprises steps of: applying a third voltage to the bit-line to perform a small voltage difference across the bit-line and the drain of the gFET, applying a second voltage to the word-line to turn on the gFET, and comparing the current through the switching resistor with the current through the reference resistor so as to read the data stored in the memory cell.

摘要翻译： 随机存取存储器包括以位线和字线排列的多个存储单元。 每个存储单元包括包括栅极，源极和漏极的绿色晶体管（gFET）; 开关电阻器，包括第一端子和第二端子; 以及包括第三端子和第四端子的参考电阻器。 开关电阻器和第三端子的第一端子连接到位线，开关电阻器的第二端子连接到gFET的第一源极，参考电阻器的第四端子连接到第二源极 gFET和gFET的栅极连接到字线。 操作RRAM的方法包括写入操作和读取操作。写入操作包括以下步骤：向位线施加第一电压以在gFET的位线和漏极之间执行大的电压差，施加 第二电压到gFET的栅极，瞬时导通gFET，并且大电流脉冲流过开关电阻器以改变电阻状态。 读取操作包括以下步骤：将第三电压施加到位线，以在gFET的位线和漏极之间执行小的电压差，向字线施加第二电压以导通gFET;以及 将通过开关电阻的电流与通过参考电阻的电流进行比较，以读取存储在存储单元中的数据。

公开(公告)号：US20110018608A1

公开(公告)日：2011-01-27

申请号：US12842903

申请日：2010-07-23

申请人： Min-hwa Chi ,  Lihying Ching ,  Deyuan Xiao

发明人： Min-hwa Chi ,  Lihying Ching ,  Deyuan Xiao

IPC分类号： H03K17/60 ,  H01L21/331 ,  H01L29/70 ,  G05F1/10

CPC分类号： H01L29/66325 ,  G05F3/30 ,  H01L21/26586 ,  H01L21/8228 ,  H01L21/84 ,  H01L27/082 ,  H01L27/1203 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/1095 ,  H01L29/66265 ,  H01L29/7317 ,  H01L29/7393 ,  H03K17/60

摘要： The present invention provides a bipolar transistor, a method for forming the bipolar transistor, a method for turning on the bipolar transistor, and a band-gap reference circuit, virtual ground reference circuit and double band-gap reference circuit with the bipolar transistor. The bipolar transistor includes: a Silicon-On-Insulator wafer; a base area, an emitter area and a collector area; a base area gate dielectric layer on a top silicon layer and atop the base area; a base area control-gate on the base area gate dielectric layer; an emitter electrode connected to the emitter area via a first contact; a collector electrode connected to the collector area via a second contact; and a base area control-gate electrode connected to the base area control-gate via a third contact. Processes of forming the bipolar transistor are fully compatible with traditional standard CMOS processes; and the base current to turn on the bipolar transistor is based on the GIDL current and formed by applying a voltage to the base area control-gate electrode without any need of contact.

摘要翻译： 本发明提供一种双极晶体管，双极型晶体管的形成方法，双极型晶体管的导通方法，带隙基准电路，虚拟接地参考电路以及双极性晶体管的双带隙基准电路。 双极晶体管包括：绝缘体上硅晶片; 基极区域，发射极区域和集电极区域; 位于顶部硅层上的基极区电介质层，并在基底区域顶部; 基区栅极电介质层上的基区控制栅极; 经由第一触点连接到发射极区域的发射极; 集电极，经由第二触点连接到集电区; 以及通过第三触点连接到基区控制门的基区控制栅电极。 形成双极晶体管的工艺与传统的标准CMOS工艺完全兼容; 并且用于导通双极晶体管的基极电流基于GIDL电流并且通过向基极区域控制栅电极施加电压而形成，而不需要接触。

公开(公告)号：US08969108B2

公开(公告)日：2015-03-03

申请号：US13881723

申请日：2011-02-10

申请人： Deyuan Xiao ,  Richard Rugin Chang

发明人： Deyuan Xiao ,  Richard Rugin Chang

IPC分类号： H01L29/06 ,  H01L33/64 ,  H01L33/00 ,  H01L21/20

CPC分类号： H01L33/385 ,  H01L21/2007 ,  H01L33/007 ,  H01L33/0079 ,  H01L33/12 ,  H01L33/62 ,  H01L33/641

摘要： A light emitting diode (LED) and a forming method thereof are provided. The method for forming the LED includes: providing a semiconductor substrate (20) and a sapphire substrate (30) respectively, wherein a first bonding layer (21) is formed on the silicon substrate (20), and a sacrificial layer (32), an LED die (33) and a second bonding layer (35) are formed in turn on the sapphire substrate (30); bonding the first bonding layer (21) and the second bonding layer (35); removing the sacrificial layer (32) and lifting off the sapphire substrate (30). The method increases the effective lighting area of the LED, improves heat radiation, and enhances lighting efficiency.

摘要翻译： 提供一种发光二极管（LED）及其形成方法。 形成LED的方法包括：分别提供半导体衬底（20）和蓝宝石衬底（30），其中在硅衬底（20）上形成第一接合层（21）和牺牲层（32）， 依次在蓝宝石衬底（30）上形成LED管芯（33）和第二接合层（35）; 接合第一接合层（21）和第二接合层（35）; 去除牺牲层（32）并提起蓝宝石衬底（30）。 该方法增加了LED的有效照明面积，改善了散热，提高了照明效率。

公开(公告)号：US08833431B2

公开(公告)日：2014-09-16

申请号：US13059634

申请日：2010-12-30

申请人： Deyuan Xiao ,  Richard Rugin Chang ,  Mengjan Cherng ,  Qing Rao

发明人： Deyuan Xiao ,  Richard Rugin Chang ,  Mengjan Cherng ,  Qing Rao

IPC分类号： B22D17/00

CPC分类号： C22C21/00 ,  B22D17/00 ,  C22C1/026 ,  C22C1/1036 ,  C22C26/00 ,  F21V29/85 ,  H01L23/3733 ,  H01L23/3736 ,  H01L33/641 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2933/0075 ,  H01L2924/00

摘要： The present invention discloses an aluminum alloy material, which is made of raw material of aluminum alloy. The raw material of aluminum alloy consists of the following constituents by percentage of weight: graphene: 0.1%˜1%, carbon nano tube: 1%˜5%, the rest being Al. The aluminum alloy material of the present invention has a good performance of heat dissipation, the thermal conductivity is higher than 200 W/m. Meanwhile, the present invention further provides a method of manufacturing aluminum alloy backboard, in which method, the raw material of aluminum alloy is heated and melted in a heating furnace, afterwards, the raw material of aluminum alloy after melting is formed into an aluminum alloy backboard by die-casting, in this way, the utilization rate of material is increased and the manufacturing cost of the backboard is reduced.

摘要翻译： 本发明公开了一种由铝合金原料制成的铝合金材料。 铝合金原料由以下重量百分比组成：石墨烯：0.1％〜1％，碳纳米管：1％〜5％，其余为Al。 本发明的铝合金材料具有良好的散热性能，导热系数高于200W / m。 同时，本发明还提供一种制造铝合金背板的方法，其中将铝合金原料在加热炉中加热熔化，之后将熔融后的铝合金原料形成为铝合金 通过压铸，通过这种方式，材料的利用率提高，背板的制造成本降低。

公开(公告)号：US08264042B2

公开(公告)日：2012-09-11

申请号：US12810574

申请日：2010-02-11

申请人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhong Ying Xue

发明人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhong Ying Xue

IPC分类号： H01L27/12

CPC分类号： H01L29/78696 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1203 ,  H01L29/42392

摘要： A hybrid orientation accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of p-type Si(110) and n-type Si(100), respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. The device structure according to the prevent invention is quite simple, compact and highly integrated. In an accumulation mode, current flows through the overall racetrack-shaped channel. The disclosed device results in high carrier mobility. Meanwhile polysilicon gate depletion and short channel effects are prevented, and threshold voltage is increased.

摘要翻译： 混合取向累积模式GAA（Gate-All-Around）CMOSFET包括具有第一通道的PMOS区域，具有第二通道的NMOS区域和栅极区域。 第一通道和第二通道具有跑道形横截面并分别由p型Si（110）和n型Si（100）形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。 根据本发明的装置结构相当简单，紧凑且高度集成。 在积累模式中，电流流过整个跑道状通道。 所公开的装置导致高载流子迁移率。 同时防止多晶硅栅极耗尽和短沟道效应，并且阈值电压增加。

公开(公告)号：US08233312B2

公开(公告)日：2012-07-31

申请号：US12934745

申请日：2010-07-14

申请人： Deyuan Xiao ,  Xiaolu Huang ,  Jing Chen ,  Xi Wang

发明人： Deyuan Xiao ,  Xiaolu Huang ,  Jing Chen ,  Xi Wang

IPC分类号： G11C11/24

CPC分类号： H01L29/7841 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/10802

摘要： The present invention discloses a DRAM cell utilizing floating body effect and a manufacturing method thereof. The DRAM cell includes a first N type semiconductor region provided on a buried oxide layer, a P type semiconductor region provided on the first N type semiconductor region, a gate region provided on the P type semiconductor region, and an electrical isolation region surrounding the P type semiconductor region and the N type semiconductor region. A diode is taken as a storage node. Via a tunneling effect between bands, holes gather in the floating body, which is defined as a first storage state; via forward bias of PN junction, holes are emitted out from the floating body or electrons are injected into the floating body, which is defined as a second storage state. The present invention provides a highly efficient DRAM cell utilizing floating body effect with high density, which has low power consumption, has simple manufacturing process, and is compatible to the conventional CMOS and conventional logic circuit manufacturing process.

摘要翻译： 本发明公开了一种利用浮体效应的DRAM单元及其制造方法。 DRAM单元包括设置在掩埋氧化物层上的第一N型半导体区域，设置在第一N型半导体区域上的P型半导体区域，设置在P型半导体区域上的栅极区域和围绕P型半导体区域的电隔离区域 型半导体区域和N型半导体区域。 二极管作为存储节点。 通过带之间的隧道效应，孔被聚集在浮体中，其被定义为第一储存状态; 通过PN结的正向偏压，空穴从浮体发射出来，或者电子被注入浮动体，其被定义为第二存储状态。 本发明提供一种利用高密度的浮体效应的高效率DRAM单元，其具有低功耗，制造工艺简单，并且与常规CMOS和常规逻辑电路制造工艺兼容。