公开(公告)号：US20120140543A1

公开(公告)日：2012-06-07

申请号：US13223165

申请日：2011-08-31

申请人： Ming Liu ,  Qingyun Zuo ,  Shibing Long ,  Changqing Xie ,  Zongliang Huo

发明人： Ming Liu ,  Qingyun Zuo ,  Shibing Long ,  Changqing Xie ,  Zongliang Huo

IPC分类号： G11C17/06 ,  H01L21/8246

CPC分类号： H01L29/872 ,  G11C17/06 ,  H01L27/1021 ,  H01L29/861

摘要： The present invention relates to a one time programming memory and method of storage and manufacture of the same. It belongs to microelectronic memory technology and manufacture field. The one time programming memory comprises a diode (10) having a unidirectional conducting rectification characteristic and a variable-resistance memory (20) having a bipolar conversion characteristic. The diode (10) having the unidirectional conducting rectification characteristic and the variable-resistance memory (20) having the bipolar conversion characteristic are connected in series. The one time programming memory device of the present invention takes the bipolar variable-resistance memory (20) as a storage unit, programming the bipolar variable-resistance memory (20) into different resistance states so as to carry out multilevel storage, and takes the unidirectional conducting rectification diode (10) as a gating unit. The rectification characteristic of unidirectional conducting rectification diode (10) can not only enable the bipolar variable-resistance storage (20) to be programmed only once but also inhibit crosstalk in a cross-array structure. The one time programming memory of the present invention is suitable to integration of the cross-array structure. It has the advantages like a simple structure, easy integration and high density. It can achieve multilevel storage and reduce the cost, which contribute to widely spreading and application of the present invention.

摘要翻译： 本发明涉及一次性编程存储器及其存储和制造方法。 属于微电子存储技术和制造领域。 一次性编程存储器包括具有单向导通整流特性的二极管（10）和具有双极转换特性的可变电阻存储器（20）。 具有单向导通整流特性的二极管（10）和具有双极转换特性的可变电阻存储器（20）串联连接。 本发明的一次性编程存储装置将双极可变电阻存储器（20）作为存储单元，将双极可变电阻存储器（20）编程成不同的电阻状态，以进行多级存储，并且 单向导通整流二极管（10）作为选通单元。 单向导通整流二极管（10）的整流特性不仅可以使双极可变电阻存储器（20）只编程一次，而且可以抑制交叉阵列结构中的串扰。 本发明的一次性编程存储器适合于集成交叉阵列结构。 具有结构简单，易于集成，密度高等优点。 它可以实现多级存储并降低成本，这有助于本发明的广泛推广和应用。

公开(公告)号：US08531861B2

公开(公告)日：2013-09-10

申请号：US13223165

申请日：2011-08-31

申请人： Ming Liu ,  Qingyun Zuo ,  Shibing Long ,  Changqing Xie ,  Zongliang Huo

发明人： Ming Liu ,  Qingyun Zuo ,  Shibing Long ,  Changqing Xie ,  Zongliang Huo

IPC分类号： G11C17/00

CPC分类号： H01L29/872 ,  G11C17/06 ,  H01L27/1021 ,  H01L29/861

摘要： One time programming memory and methods of storage and manufacture of the same are provided. Examples relate to microelectronic memory technology and manufacture. The one time programming memory includes a diode (10) having a unidirectional conducting rectification characteristic and a variable-resistance memory (20) having a bipolar conversion characteristic. The diode (10) having the unidirectional conducting rectification characteristic and the variable-resistance memory (20) having the bipolar conversion characteristic are connected in series. The one time programming memory device of this example takes the bipolar variable-resistance memory (20) as a storage unit, programming the bipolar variable-resistance memory (20) into different resistance states so as to carry out multilevel storage, and takes the unidirectional conducting rectification diode (10) as a gating unit. The rectification characteristic of unidirectional conducting rectification diode (10) can not only enable the bipolar variable-resistance storage (20) to be programmed only once but also inhibit crosstalk in a cross-array structure.

摘要翻译： 提供了一次编程存储器及其存储和制造方法。 实例涉及微电子存储器技术和制造。 一次编程存储器包括具有单向导通整流特性的二极管（10）和具有双极转换特性的可变电阻存储器（20）。 具有单向导通整流特性的二极管（10）和具有双极转换特性的可变电阻存储器（20）串联连接。 该实施例的一次性编程存储器件将双极可变电阻存储器（20）作为存储单元，将双极可变电阻存储器（20）编程成不同的电阻状态，以执行多级存储，并且采用单向 导通整流二极管（10）作为选通单元。 单向导通整流二极管（10）的整流特性不仅可以使双极可变电阻存储器（20）只编程一次，而且可以抑制交叉阵列结构中的串扰。

公开(公告)号：US20120281452A1

公开(公告)日：2012-11-08

申请号：US13502832

申请日：2011-06-30

申请人： Zongliang Huo ,  Ming Liu ,  Manhong Zhang ,  Yanhua Wang ,  Shibing Long

发明人： Zongliang Huo ,  Ming Liu ,  Manhong Zhang ,  Yanhua Wang ,  Shibing Long

IPC分类号： H01L45/00 ,  G11C11/00

CPC分类号： H01L27/2409 ,  H01L27/2463

摘要： The present disclosure provides a resistive random memory cell and a resistive random memory. The resistive random memory cell comprises an upper electrode, a resistive layer, an intermediate electrode, an asymmetric tunneling barrier layer, and a lower electrode. The upper electrode, the resistive layer, and the intermediate electrode constitute a resistive storage portion. The intermediate electrode, the asymmetric tunneling barrier layer, and the lower electrode constitute a selection portion. The resistive storage portion and the selection portion share the intermediate electrode. The selection portion may be disposed above or under the resistive storage portion. The asymmetric tunneling barrier layer comprises at least two materials having different barrier heights, and is configured for rectifying forward tunneling current and reverse tunneling current flowing through the resistive random memory cell. The present disclosure uses the asymmetric tunneling barrier layer for rectifying, so as to enable selection of the resistive random memory cell. The method for manufacturing the asymmetric tunneling barrier layer does not involve doping or high-temperature annealing processes, and the thickness of the asymmetric tunneling barrier layer is relatively small, which helps 3D high-density integration of the resistive random memory.

摘要翻译： 本公开提供了电阻随机存储器单元和电阻随机存储器。 电阻随机存储单元包括上电极，电阻层，中间电极，不对称隧道势垒层和下电极。 上电极，电阻层和中间电极构成电阻存储部。 中间电极，不对称隧道势垒层和下电极构成选择部分。 电阻存储部分和选择部分共享中间电极。 选择部分可以设置在电阻存储部分的上方或下方。 非对称隧道势垒层包括具有不同势垒高度的至少两种材料，并且被配置用于整流流过电阻随机存储单元的正向隧穿电流和反向隧穿电流。 本公开使用非对称隧道势垒层进行整流，以便能够选择电阻随机存储单元。 制造不对称隧道势垒层的方法不涉及掺杂或高温退火工艺，并且不对称隧道势垒层的厚度相对较小，这有助于电阻随机存储器的3D高密度集成。

公开(公告)号：US08705274B2

公开(公告)日：2014-04-22

申请号：US13376925

申请日：2011-06-30

申请人： Ming Liu ,  Chenxi Zhu ,  Zongliang Huo ,  Feng Yan ,  Qin Wang ,  Shibing Long

发明人： Ming Liu ,  Chenxi Zhu ,  Zongliang Huo ,  Feng Yan ,  Qin Wang ,  Shibing Long

IPC分类号： G11C16/04 ,  H01L21/336

CPC分类号： H01L27/11582

摘要： The present disclosure relates to the field of microelectronics manufacture and memories. A three-dimensional multi-bit non-volatile memory and a method for manufacturing the same are disclosed. The memory comprises a plurality of memory cells constituting a memory array. The memory array may comprise: a gate stack structure; periodically and alternately arranged gate stack regions and channel region spaces; gate dielectric layers for discrete charge storage; periodically arranged channel regions; source doping regions and drain doping regions symmetrically arranged to each other; bit lines led from the source doping regions and the drain doping regions; and word lines led from the gate stack regions. The gate dielectric layers for discrete charge storage can provide physical storage spots to achieve single-bit or multi-bit operations, so as to achieve a high storage density. According to the present disclosure, the localized charge storage characteristic of the charge trapping layer and characteristics such as a longer effective channel length and a higher density of a vertical memory structure are utilized, to provide multiple storage spots in a single memory cell. Therefore, the storage density is improved while good performances such as high speed are ensured.

摘要翻译： 本公开涉及微电子制造领域和存储器。 公开了一种三维多位非易失性存储器及其制造方法。 存储器包括构成存储器阵列的多个存储单元。 存储器阵列可以包括：栅极堆叠结构; 定期和交替布置的栅极堆叠区域和沟道区域空间; 用于离散电荷存储的栅极电介质层; 定期布置的通道区域; 源极掺杂区域和漏极掺杂区域彼此对称布置; 源极掺杂区域和漏极掺杂区域引出的位线; 和从栅极堆栈区域引出的字线。 用于离散电荷存储的栅极电介质层可以提供物理存储点以实现单位或多位操作，从而实现高存储密度。 根据本公开，利用电荷俘获层的局部电荷存储特性以及垂直存储器结构的较长有效沟道长度和较高密度等特征，以在单个存储单元中提供多个存储点。 因此，存储密度得到改善，同时保证了诸如高速的良好性能。

公开(公告)号：US08665631B2

公开(公告)日：2014-03-04

申请号：US13502832

申请日：2011-06-30

申请人： Zongliang Huo ,  Ming Liu ,  Manhong Zhang ,  Yanhua Wang ,  Shibing Long

发明人： Zongliang Huo ,  Ming Liu ,  Manhong Zhang ,  Yanhua Wang ,  Shibing Long

IPC分类号： G11C11/00

CPC分类号： H01L27/2409 ,  H01L27/2463

摘要： The present disclosure provides a resistive random memory cell and a resistive random memory. The resistive random memory cell comprises an upper electrode, a resistive layer, an intermediate electrode, an asymmetric tunneling barrier layer, and a lower electrode. The upper electrode, the resistive layer, and the intermediate electrode constitute a resistive storage portion. The intermediate electrode, the asymmetric tunneling barrier layer, and the lower electrode constitute a selection portion. The resistive storage portion and the selection portion share the intermediate electrode. The selection portion may be disposed above or under the resistive storage portion. The asymmetric tunneling barrier layer comprises at least two materials having different barrier heights, and is configured for rectifying forward tunneling current and reverse tunneling current flowing through the resistive random memory cell. The present disclosure uses the asymmetric tunneling barrier layer for rectifying, so as to enable selection of the resistive random memory cell. The method for manufacturing the asymmetric tunneling barrier layer does not involve doping or high-temperature annealing processes, and the thickness of the asymmetric tunneling barrier layer is relatively small, which helps 3D high-density integration of the resistive random memory.

摘要翻译： 本公开提供了电阻随机存储器单元和电阻随机存储器。 电阻随机存储单元包括上电极，电阻层，中间电极，不对称隧道势垒层和下电极。 上电极，电阻层和中间电极构成电阻存储部。 中间电极，不对称隧道势垒层和下电极构成选择部分。 电阻存储部分和选择部分共享中间电极。 选择部分可以设置在电阻存储部分的上方或下方。 非对称隧道势垒层包括具有不同势垒高度的至少两种材料，并且被配置用于整流流过电阻随机存储单元的正向隧穿电流和反向隧穿电流。 本公开使用非对称隧道势垒层进行整流，以便能够选择电阻随机存储单元。 制造不对称隧道势垒层的方法不涉及掺杂或高温退火工艺，并且不对称隧道势垒层的厚度相对较小，这有助于电阻随机存储器的3D高密度集成。

公开(公告)号：US20120275220A1

公开(公告)日：2012-11-01

申请号：US13376925

申请日：2011-06-30

申请人： Ming Liu ,  Chenxi Zhu ,  Zongliang Huo ,  Feng Yan ,  Qin Wang ,  Shibing Long

发明人： Ming Liu ,  Chenxi Zhu ,  Zongliang Huo ,  Feng Yan ,  Qin Wang ,  Shibing Long

IPC分类号： H01L29/792 ,  G11C16/14 ,  G11C16/04 ,  H01L21/336

CPC分类号： H01L27/11582

摘要： The present disclosure relates to the field of microelectronics manufacture and memories. A three-dimensional multi-bit non-volatile memory and a method for manufacturing the same are disclosed. The memory comprises a plurality of memory cells constituting a memory array. The memory array may comprise: a gate stack structure; periodically and alternately arranged gate stack regions and channel region spaces; gate dielectric layers for discrete charge storage; periodically arranged channel regions; source doping regions and drain doping regions symmetrically arranged to each other; bit lines led from the source doping regions and the drain doping regions; and word lines led from the gate stack regions. The gate dielectric layers for discrete charge storage can provide physical storage spots to achieve single-bit or multi-bit operations, so as to achieve a high storage density. According to the present disclosure, the localized charge storage characteristic of the charge trapping layer and characteristics such as a longer effective channel length and a higher density of a vertical memory structure are utilized, to provide multiple storage spots in a single memory cell. Therefore, the storage density is improved while good performances such as high speed are ensured.

摘要翻译： 本公开涉及微电子制造领域和存储器。 公开了一种三维多位非易失性存储器及其制造方法。 存储器包括构成存储器阵列的多个存储单元。 存储器阵列可以包括：栅极堆叠结构; 定期和交替布置的栅极堆叠区域和沟道区域空间; 用于离散电荷存储的栅极电介质层; 定期布置的通道区域; 源极掺杂区域和漏极掺杂区域彼此对称布置; 源极掺杂区域和漏极掺杂区域引出的位线; 和从栅极堆栈区域引出的字线。 用于离散电荷存储的栅极电介质层可以提供物理存储点以实现单位或多位操作，从而实现高存储密度。 根据本公开，利用电荷俘获层的局部电荷存储特性以及垂直存储器结构的较长有效沟道长度和较高密度等特征，以在单个存储单元中提供多个存储点。 因此，存储密度得到改善，同时保证了诸如高速的良好性能。

公开(公告)号：US09070872B2

公开(公告)日：2015-06-30

申请号：US13880641

申请日：2011-06-30

申请人： Zongliang Huo ,  Ming Liu

发明人： Zongliang Huo ,  Ming Liu

IPC分类号： H01L21/336 ,  H01L45/00 ,  H01L27/06 ,  H01L27/10 ,  H01L27/24

CPC分类号： H01L45/00 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1226 ,  H01L45/14 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

摘要： The present disclosure provides a method for manufacturing a three-dimensional semiconductor memory device. In the method, a storage array is divided into a plurality of storage sub-arrays. As a result, a respective via of each storage sub-array can be etched respectively, which is different from the prior art, where a via for a bottom electrode of a plurality of layers of resistive cells is etched at one time. The vias are filled with metal so that storage sub-arrays are connected with each other. The method for manufacturing the three-dimensional semiconductor memory device according to the present disclosure can substantially reduce process complexity and difficulty of etching process in high-density integration, and also improve a number of layers of the resistive cells integrated in the storage array.

摘要翻译： 本公开提供了一种用于制造三维半导体存储器件的方法。 在该方法中，存储阵列被分成多个存储子阵列。 结果，可以分别蚀刻每个存储子阵列的相应通孔，这与现有技术不同，其中一次蚀刻多层电阻单元的底部电极的通孔。 通孔用金属填充，使得存储子阵列彼此连接。 根据本公开的制造三维半导体存储器件的方法可以大大降低高密度集成中的工艺复杂度和蚀刻工艺的难度，并且还可以改善集成在存储阵列中的电阻式电池的多个层。

公开(公告)号：US20120248503A1

公开(公告)日：2012-10-04

申请号：US13512643

申请日：2011-06-30

申请人： Zongliang Huo ,  Ming Liu

发明人： Zongliang Huo ,  Ming Liu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7841 ,  Y10S438/933 ,  Y10S438/938

摘要： A semiconductor memory cell, a semiconductor memory device, and a method for manufacturing the same are disclosed. The semiconductor memory cell may comprise: a substrate; a channel region on the substrate; a gate region above the channel region; a source region and a drain region on the substrate and at opposite sides of the channel region; and a buried layer, which is disposed between the substrate and the channel region and comprises a material having a forbidden band narrower than that of a material for the channel region material. The buried layer material has a forbidden band narrower than that of the channel region material, so that a hole barrier is formed in the buried layer. Due to the barrier, it is difficult for holes stored in the buried layer to leak out, resulting in an improved information holding duration of the memory cell utilizing the floating-body effect.

摘要翻译： 公开了半导体存储单元，半导体存储器件及其制造方法。 半导体存储单元可以包括：衬底; 衬底上的沟道区; 沟道区域上方的栅极区域; 源极区域和漏极区域，并且位于沟道区域的相对侧; 以及掩埋层，其设置在基板和沟道区域之间，并且包括具有比用于沟道区域材料的材料窄的带的禁带的材料。 掩埋层材料具有比沟道区域材料窄的禁带，使得在掩埋层中形成空穴阻挡层。 由于屏障，存储在掩埋层中的孔难以泄漏出来，导致利用浮体效应改善存储单元的信息保持持续时间。

公开(公告)号：US09000409B2

公开(公告)日：2015-04-07

申请号：US13376276

申请日：2011-06-30

申请人： Zongliang Huo ,  Ming Liu

发明人： Zongliang Huo ,  Ming Liu

IPC分类号： H01L47/00 ,  H01L27/24 ,  H01L45/00

CPC分类号： H01L27/249 ,  H01L27/2454 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

摘要： The present application discloses a 3D semiconductor memory device having 1T1R memory configuration based on a vertical-type gate-around transistor, and a manufacturing method thereof. A on/off current ratio can be well controlled by changing a width and a length of a channel of the gate-around transistor, so as to facilitate multi-state operation of the 1T1R memory cell. Moreover, the vertical transistor has a smaller layout size than a horizontal transistor, so as to reduce the layout size effectively. Thus, the 3D semiconductor memory device can be integrated into an array with a high density.

摘要翻译： 本申请公开了一种具有基于垂直型栅极晶体管的1T1R存储器配置的3D半导体存储器件及其制造方法。 可以通过改变栅极周围晶体管的沟道的宽度和长度来良好地控制开/关电流比，以便于1T1R存储单元的多状态操作。 此外，垂直晶体管具有比水平晶体管更小的布局尺寸，以便有效地减小布局尺寸。 因此，3D半导体存储器件可以集成到具有高密度的阵列中。

公开(公告)号：US08927963B2

公开(公告)日：2015-01-06

申请号：US13512643

申请日：2011-06-30

申请人： Zongliang Huo ,  Ming Liu

发明人： Zongliang Huo ,  Ming Liu

IPC分类号： H01L29/06 ,  H01L31/00 ,  H01L29/78

CPC分类号： H01L29/7841 ,  Y10S438/933 ,  Y10S438/938

摘要： A semiconductor memory cell, a semiconductor memory device, and a method for manufacturing the same are disclosed. The semiconductor memory cell may comprise: a substrate; a channel region on the substrate; a gate region above the channel region; a source region and a drain region on the substrate and at opposite sides of the channel region; and a buried layer, which is disposed between the substrate and the channel region and comprises a material having a forbidden band narrower than that of a material for the channel region material. The buried layer material has a forbidden band narrower than that of the channel region material, so that a hole barrier is formed in the buried layer. Due to the barrier, it is difficult for holes stored in the buried layer to leak out, resulting in an improved information holding duration of the memory cell utilizing the floating-body effect.

摘要翻译： 公开了半导体存储单元，半导体存储器件及其制造方法。 半导体存储单元可以包括：衬底; 衬底上的沟道区; 沟道区域上方的栅极区域; 源极区域和漏极区域，并且位于沟道区域的相对侧; 以及掩埋层，其设置在基板和沟道区域之间，并且包括具有比用于沟道区域材料的材料窄的带的禁带的材料。 掩埋层材料具有比沟道区域材料窄的禁带，使得在掩埋层中形成空穴阻挡层。 由于屏障，存储在掩埋层中的孔难以泄漏出来，导致利用浮体效应改善存储单元的信息保持持续时间。