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205 条记录 (耗时 0.029 秒)

    Method to solve via poisoning for porous low-k dielectric
    2.
    发明授权
    Method to solve via poisoning for porous low-k dielectric 失效
    解决多孔低介电常数中毒的方法

    公开(公告)号：US06878615B2

    公开(公告)日：2005-04-12

    申请号：US09863224

    申请日：2001-05-24

    申请人： Ming-Hsing Tsai ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

    发明人： Ming-Hsing Tsai ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

    IPC分类号： H01L21/768 ,  H01L21/4763

    CPC分类号： H01L21/76844 ,  H01L21/76807 ,  H01L21/76831 ,  H01L2221/1063

    摘要： A method of forming a via in a low-k dielectric material and without the attendant via poisoning problem, or a dual damascene structure formed in the same dielectric and without the same problem are disclosed. The vertical walls of the via opening are first lined with a low-k protection layer and then covered with a barrier layer in order to prevent outgassing from the low-k dielectric material when copper is deposited into the via opening. In the case of a dual damascene structure, it is sufficient that the hole opening underlying the trench opening is first lined with the low-k protection layer. The resulting via or dual damascene structure is free of poisoned metal and, therefore, more reliable.

    摘要翻译： 公开了一种在低k电介质材料中形成通孔并且不伴随通过中毒问题的方法，或者形成在相同电介质中并且没有相同问题的双镶嵌结构。 通孔开口的垂直壁首先衬有低k保护层，然后被阻挡层覆盖，以便当铜沉积到通孔中时，防止从低k电介质材料脱气。 在双镶嵌结构的情况下，沟槽开口下方的开孔首先衬有低k保护层就足够了。 所得到的通孔或双镶嵌结构没有中毒金属，因此更可靠。

    Method to solve via poisoning for porous low-k dielectric
    3.
    发明授权
    Method to solve via poisoning for porous low-k dielectric 有权
    解决多孔低介电常数中毒的方法

    公开(公告)号：US07250683B2

    公开(公告)日：2007-07-31

    申请号：US11056758

    申请日：2005-02-11

    申请人： Ming-Hsing Tsai ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

    发明人： Ming-Hsing Tsai ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L21/76844 ,  H01L21/76807 ,  H01L21/76831 ,  H01L2221/1063

    摘要： A method of forming a via in a low-k dielectric material and without the attendant via poisoning problem, or a dual damascene structure formed in the same dielectric and without the same problem are disclosed. The vertical walls of the via opening are first lined with a low-k protection layer and then covered with a barrier layer in order to prevent outgassing from the low-k dielectric material when copper is deposited into the via opening. In the case of a dual damascene structure, it is sufficient that the hole opening underlying the trench opening is first lined with the low-k protection layer. The resulting via or dual damascene structure is free of poisoned metal and, therefore, more reliable.

    摘要翻译： 公开了一种在低k电介质材料中形成通孔并且不伴随通过中毒问题的方法，或者形成在相同电介质中并且没有相同问题的双镶嵌结构。 通孔开口的垂直壁首先衬有低k保护层，然后被阻挡层覆盖，以便当铜沉积到通孔中时，防止从低k电介质材料脱气。 在双镶嵌结构的情况下，沟槽开口下方的开孔首先衬有低k保护层就足够了。 所得到的通孔或双镶嵌结构没有中毒金属，因此更可靠。

    Loadlock
    6.
    发明申请
    Loadlock 审中-公开
    负载锁

    公开(公告)号：US20050097769A1

    公开(公告)日：2005-05-12

    申请号：US10668291

    申请日：2003-09-24

    申请人： Jing-Cheng Lin ,  Shing-Chyang Pan ,  Hsien-Ming Lee ,  Hung-Wen Su ,  Shih-Wei Chou ,  Ming-Hsing Tsai ,  Shau-Lin Shue

    发明人： Jing-Cheng Lin ,  Shing-Chyang Pan ,  Hsien-Ming Lee ,  Hung-Wen Su ,  Shih-Wei Chou ,  Ming-Hsing Tsai ,  Shau-Lin Shue

    IPC分类号： H01L21/677 ,  F26B13/30

    CPC分类号： H01L21/67781

    摘要： A loadlock. The loadlock for wafers includes a chamber, a pedestal, a retractable shaft, and a bellows. The chamber has a plurality of walls and a bottom surface. The pedestal supports a cassette and is disposed in the chamber. The retractable shaft has a top end and a bottom end. The top end is connected to the pedestal and the bottom end is connected to the bottom surface as a reference for positioning the pedestal. The bellows has a first end and a second end. The first end is disposed on the pedestal and the second end is sealed at the bottom end of the retractable shaft. Preferably, the retractable shaft is fully enclosed by the bellows.

    摘要翻译： 一个加载锁 用于晶片的负荷锁包括一个腔室，一个基座，一个伸缩轴和一个波纹管。 腔室具有多个壁和底面。 基座支撑盒并设置在腔室中。 伸缩轴具有顶端和底端。 顶端连接到基座，底端连接到底面作为基座的基准。 波纹管具有第一端和第二端。 第一端设置在基座上，第二端在可伸缩轴的底端被密封。 优选地，可伸缩轴被波纹管完全包围。

    Barrier structure for semiconductor devices
    8.
    发明授权
    Barrier structure for semiconductor devices 有权
    半导体器件的阻挡结构

    公开(公告)号：US07193327B2

    公开(公告)日：2007-03-20

    申请号：US11042396

    申请日：2005-01-25

    申请人： Chen-Hua Yu ,  Shing-Chyang Pan ,  Shau-Lin Shue ,  Ching-Hua Hsieh ,  Cheng-Lin Huang ,  Hsien-Ming Lee ,  Jing-Cheng Lin

    发明人： Chen-Hua Yu ,  Shing-Chyang Pan ,  Shau-Lin Shue ,  Ching-Hua Hsieh ,  Cheng-Lin Huang ,  Hsien-Ming Lee ,  Jing-Cheng Lin

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L23/53295 ,  H01L21/76805 ,  H01L21/76844 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An opening in a dielectric layer having a unique barrier layer structure is provided. In an embodiment, the opening is a via and a trench. The barrier layer, which may comprise one or more barrier layers, is formed such that the ratio of the thickness of the barrier layers along a sidewall approximately midway between the bottom of the trench and the top of the dielectric layer to the thickness of the barrier layers along the bottom of the trench is greater than about 0.55. In another embodiment, the ratio of the thickness of the barrier layers along a sidewall approximately midway between the bottom of the trench and the top of the dielectric layer to the thickness of the barrier layers along the bottom of the via is greater than about 1.0. An underlying conductive layer may be recessed.

    摘要翻译： 提供具有独特的阻挡层结构的电介质层中的开口。 在一个实施例中，开口是通孔和沟槽。 可以形成阻挡层，其可以包括一个或多个阻挡层，使得阻挡层的厚度在沟槽的底部和电介质层的顶部之间的大致中间的侧壁与屏障的厚度之比 沿着沟槽底部的层大于约0.55。 在另一个实施例中，沿着沟槽底部和电介质层的顶部之间大约中间的侧壁的阻挡层的厚度与通孔底部的阻挡层的厚度之比大于约1.0。 潜在的导电层可以凹入。

    Barrier structure for semiconductor devices
    9.
    发明申请
    Barrier structure for semiconductor devices 有权
    半导体器件的阻挡结构

    公开(公告)号：US20060163746A1

    公开(公告)日：2006-07-27

    申请号：US11042396

    申请日：2005-01-25

    申请人： Chen-Hua Yu ,  Shing-Chyang Pan ,  Shau-Lin Shue ,  Ching-Hua Hsieh ,  Cheng-Lin Huang ,  Hsien-Ming Lee ,  Jing-Cheng Lin

    发明人： Chen-Hua Yu ,  Shing-Chyang Pan ,  Shau-Lin Shue ,  Ching-Hua Hsieh ,  Cheng-Lin Huang ,  Hsien-Ming Lee ,  Jing-Cheng Lin

    IPC分类号： H01L23/48

    CPC分类号： H01L23/53295 ,  H01L21/76805 ,  H01L21/76844 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An opening in a dielectric layer having a unique barrier layer structure is provided. In an embodiment, the opening is a via and a trench. The barrier layer, which may comprise one or more barrier layers, is formed such that the ratio of the thickness of the barrier layers along a sidewall approximately midway between the bottom of the trench and the top of the dielectric layer to the thickness of the barrier layers along the bottom of the trench is greater than about 0.55. In another embodiment, the ratio of the thickness of the barrier layers along a sidewall approximately midway between the bottom of the trench and the top of the dielectric layer to the thickness of the barrier layers along the bottom of the via is greater than about 1.0. An underlying conductive layer may be recessed.

    摘要翻译： 提供具有独特的阻挡层结构的电介质层中的开口。 在一个实施例中，开口是通孔和沟槽。 可以形成阻挡层，其可以包括一个或多个阻挡层，使得阻挡层的厚度在沟槽的底部和电介质层的顶部之间的大致中间的侧壁与屏障的厚度之比 沿着沟槽底部的层大于约0.55。 在另一个实施例中，沿着沟槽底部和电介质层的顶部之间大约中间的侧壁的阻挡层的厚度与通孔底部的阻挡层的厚度之比大于约1.0。 潜在的导电层可以凹入。

    Method of fabricating barrier adhesion to low-k dielectric layers in a copper damascene process
    10.
    发明授权
    Method of fabricating barrier adhesion to low-k dielectric layers in a copper damascene process 有权
    在铜镶嵌工艺中制造对低k电介质层的屏障粘附的方法

    公开(公告)号：US06342448B1

    公开(公告)日：2002-01-29

    申请号：US09583401

    申请日：2000-05-31

    申请人： Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

    发明人： Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

    IPC分类号： H01L2144

    CPC分类号： H01L21/76846 ,  H01L21/28568 ,  H01L21/76807 ,  H01L21/76873

    摘要： A method for forming an improved TaN copper barrier for a copper damascene process is described which has improved adhesion to low-k dielectric layers and also improves the wetting of a copper seed layer deposited over it thereby improving the structure of the copper seed layer which is critical to achieving uniform, high quality electrochemical copper deposition. The copper barrier is a composite structure having an lower thin Ta rich TaN portion which mixes into and reacts with the surface of the low-k dielectric layer, forming a strongly bonded transition layer between the low-k material and the remaining portion of the barrier layer. The presence of the transition layer causes compressive film stress rather than tensile stress as found in the conventional TaN barrier. As a result, the barrier layer does not delaminate from the low-k layer during subsequent processing. A second thick central portion of the barrier layer is formed of stoichiometric TaN which benefits subsequent CMP of the copper damascene structure. An upper thin Ta portion improves barrier wetting to the copper seed layer. The three sections of the laminar barrier are sequentially deposited in a single pumpdown operation by IMP sputtering from a Ta target.

    摘要翻译： 描述了一种用于形成用于铜镶嵌工艺的改进的TaN铜阻挡层的方法，其具有改善的对低k电介质层的粘附性，并且还改善了沉积在其上的铜籽晶层的润湿，从而改善了铜籽晶层的结构， 对于实现均匀，高质量的电化学铜沉积至关重要。 铜屏障是具有较低的Ta Ta薄部分的复合结构，其混合并与低k电介质层的表面反应，在低k材料与阻挡层的剩余部分之间形成牢固结合的过渡层 层。 过渡层的存在导致压缩膜应力而不是常规TaN阻挡层中的拉伸应力。 结果，在随后的处理期间，阻挡层不会从低k层分层。 阻挡层的第二厚中心部分由化学计量的TaN形成，这有利于铜镶嵌结构的后续CMP。 上部薄的Ta部分改善了对铜种子层的屏障润湿。 层状阻挡层的三个部分通过来自Ta靶的IMP溅射在单次抽运操作中依次沉积。