公开(公告)号：US20100052188A1

公开(公告)日：2010-03-04

申请号：US12198227

申请日：2008-08-26

申请人： Mohammad Khan ,  Jun Zhai ,  Ranjit Gannamani ,  Raj N. Master

发明人： Mohammad Khan ,  Jun Zhai ,  Ranjit Gannamani ,  Raj N. Master

IPC分类号： H01L23/488 ,  H01L21/56

CPC分类号： H01L23/16 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/562 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/0401

摘要： Various semiconductor chip arrangements and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip that has an external peripheral wall to a first side of a substrate. A first metallic ring is coupled to the first side of the substrate. The first metallic ring has an internal peripheral wall that frames the semiconductor chip and is separated from the external peripheral wall by a gap. The first metallic ring has a coefficient of thermal expansion less than about 6.0 10−6 K−1.

摘要翻译： 公开了各种半导体芯片布置及其制造方法。 一方面，提供一种制造方法，其包括将具有外周壁的半导体芯片与基板的第一侧耦合。 第一金属环耦合到衬底的第一侧。 第一金属环具有框架半导体芯片并且与外周壁隔开间隙的内周壁。 第一金属环的热膨胀系数小于约6.0×10 -6 K -1。

公开(公告)号：US07923850B2

公开(公告)日：2011-04-12

申请号：US12198227

申请日：2008-08-26

申请人： Mohammad Khan ,  Jun Zhai ,  Ranjit Gannamani ,  Raj N. Master

发明人： Mohammad Khan ,  Jun Zhai ,  Ranjit Gannamani ,  Raj N. Master

IPC分类号： H01L23/448 ,  H01L21/56

CPC分类号： H01L23/16 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/562 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/0401

摘要： Various semiconductor chip arrangements and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip that has an external peripheral wall to a first side of a substrate. A first metallic ring is coupled to the first side of the substrate. The first metallic ring has an internal peripheral wall that frames the semiconductor chip and is separated from the external peripheral wall by a gap. The first metallic ring has a coefficient of thermal expansion less than about 6.0 10−6 K−1.

摘要翻译： 公开了各种半导体芯片布置及其制造方法。 一方面，提供一种制造方法，其包括将具有外周壁的半导体芯片与基板的第一侧耦合。 第一金属环耦合到衬底的第一侧。 第一金属环具有框架半导体芯片并且与外周壁隔开间隙的内周壁。 第一金属环的热膨胀系数小于约6.0×10 -6 K -1。

公开(公告)号：US20090057928A1

公开(公告)日：2009-03-05

申请号：US11849545

申请日：2007-09-04

申请人： Jun Zhai ,  Ranjit Gannamani ,  Srinivasan Parthasarathy

发明人： Jun Zhai ,  Ranjit Gannamani ,  Srinivasan Parthasarathy

IPC分类号： H01L23/18 ,  H01L21/56

CPC分类号： H01L21/563 ,  H01L23/053 ,  H01L23/3164 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/1433 ,  H01L2924/00 ,  H01L2924/00014

摘要： Various semiconductor chip underfills and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip to a substrate to leave a gap therebetween, and forming an underfill layer in the gap. The underfill layer includes a first plurality of filler particles that have a first average size and a second plurality of filler particles that have a second average size smaller than the first average size such that the first plurality of filler particles is concentrated proximate the substrate and the second plurality of filler particles is concentrated proximate the semiconductor chip so that a bulk modulus of the underfill layer is larger proximate the substrate than proximate the semiconductor chip.

摘要翻译： 提供各种半导体芯片底层填料及其制造方法。 一方面，提供了一种制造方法，其包括将半导体芯片耦合到基板以在其间留下间隙，并在间隙中形成底部填充层。 底部填充层包括具有第一平均尺寸的第一多个填料颗粒和具有小于第一平均尺寸的第二平均尺寸的第二多个填料颗粒，使得第一多个填料颗粒在基材附近集中， 第二多个填料颗粒集中在半导体芯片附近，使得底部填充层的体积模量在靠近衬底的位置比靠近半导体芯片更大。

公开(公告)号：US07745264B2

公开(公告)日：2010-06-29

申请号：US11849545

申请日：2007-09-04

申请人： Jun Zhai ,  Ranjit Gannamani ,  Srinivasan Parthasarathy

发明人： Jun Zhai ,  Ranjit Gannamani ,  Srinivasan Parthasarathy

IPC分类号： H01L21/48 ,  H01L23/28

CPC分类号： H01L21/563 ,  H01L23/053 ,  H01L23/3164 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/1433 ,  H01L2924/00 ,  H01L2924/00014

摘要： Various semiconductor chip underfills and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip to a substrate to leave a gap therebetween, and forming an underfill layer in the gap. The underfill layer includes a first plurality of filler particles that have a first average size and a second plurality of filler particles that have a second average size smaller than the first average size such that the first plurality of filler particles is concentrated proximate the substrate and the second plurality of filler particles is concentrated proximate the semiconductor chip so that a bulk modulus of the underfill layer is larger proximate the substrate than proximate the semiconductor chip.

摘要翻译： 提供各种半导体芯片底层填料及其制造方法。 一方面，提供了一种制造方法，其包括将半导体芯片耦合到基板以在其间留下间隙，并在间隙中形成底部填充层。 底部填充层包括具有第一平均尺寸的第一多个填料颗粒和具有小于第一平均尺寸的第二平均尺寸的第二多个填料颗粒，使得第一多个填料颗粒在基材附近集中， 第二多个填料颗粒集中在半导体芯片附近，使得底部填充层的体积模量在靠近衬底的位置比靠近半导体芯片更大。

公开(公告)号：US20120056336A1

公开(公告)日：2012-03-08

申请号：US13096618

申请日：2011-04-28

申请人： Min-Shin Ou ,  Chun-Yang Lee ,  Jun Zhai

发明人： Min-Shin Ou ,  Chun-Yang Lee ,  Jun Zhai

IPC分类号： H01L23/48

CPC分类号： H01L23/562 ,  H01L23/3121 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/3511

摘要： A semiconductor structure having a ring. The semiconductor structure includes a substrate, at least one chip, and the ring. The substrate has a first surface. The chip is located on the first surface of the substrate and electrically connected to the substrate. The ring has a first portion and a second portion. In various embodiments, the first and second portions different coefficients of thermal expansion (CTE), and or different cross-sectional widths. In another embodiment, the ring includes a third portion having a CTE different from both the first and second CTEs.

摘要翻译： 具有环的半导体结构。 半导体结构包括衬底，至少一个芯片和环。 衬底具有第一表面。 芯片位于基板的第一表面上并与基板电连接。 环具有第一部分和第二部分。 在各种实施例中，第一和第二部分具有不同的热膨胀系数（CTE）和/或不同的横截面宽度。 在另一个实施例中，环包括具有不同于第一和第二CTE的CTE的第三部分。

公开(公告)号：US20090200659A1

公开(公告)日：2009-08-13

申请号：US12029305

申请日：2008-02-11

申请人： Eric Tosaya ,  Jun Zhai ,  Chia-Ken Leong ,  Tom Ley

发明人： Eric Tosaya ,  Jun Zhai ,  Chia-Ken Leong ,  Tom Ley

IPC分类号： H01L21/52 ,  H01L23/02

CPC分类号： H01L23/16 ,  H01L23/04 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/19041 ,  H01L2924/19105

摘要： Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices on the first side. A stiffener frame is coupled on the first side. The stiffener frame has first and second spaced apart opposing walls that define a channel in which the first plurality of passive devices is positioned, and a central opening that does not cover a central portion of the first side of the substrate.

摘要翻译： 提供各种半导体芯片封装及其制造方法。 一方面，提供一种制造方法，其包括提供在第一侧上具有第一侧和第一多个无源器件的衬底。 加强框架连接在第一侧上。 加强框架具有第一和第二间隔开的相对的壁，其限定了第一多个无源器件定位在其中的通道，以及不覆盖衬底的第一侧的中心部分的中心开口。

公开(公告)号：US20080284047A1

公开(公告)日：2008-11-20

申请号：US11748618

申请日：2007-05-15

申请人： Eric Tosaya ,  Jun Zhai ,  Chia-Ken Leong ,  Tom Ley

发明人： Eric Tosaya ,  Jun Zhai ,  Chia-Ken Leong ,  Tom Ley

IPC分类号： H01L23/28 ,  H01L21/00

CPC分类号： H01L23/16 ,  H01L23/053 ,  H01L23/10 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15312 ,  H01L2924/19105 ,  H01L2224/0401

摘要： Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices in the first side. A polymeric stiffener ring is formed on the first side. The stiffener ring embeds the first plurality of passive devices without covering a central portion of the first surface of the substrate. A semiconductor chip is mounted on the central portion of the first surface of the substrate.

摘要翻译： 提供各种半导体芯片封装及其制造方法。 一方面，提供一种制造方法，其包括提供在第一侧具有第一侧和第一多个无源器件的衬底。 在第一侧上形成聚合物加强环。 加强环嵌入第一多个无源器件而不覆盖衬底的第一表面的中心部分。 半导体芯片安装在基板的第一表面的中心部分上。

公开(公告)号：US07253504B1

公开(公告)日：2007-08-07

申请号：US11010784

申请日：2004-12-13

申请人： Jun Zhai ,  Jinsu Kwon ,  Richard C. Blish, II

发明人： Jun Zhai ,  Jinsu Kwon ,  Richard C. Blish, II

IPC分类号： H01L23/48 ,  H01L23/12 ,  H05K1/11 ,  H01R12/04

CPC分类号： H05K3/4641 ,  H01L21/563 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/3025 ,  H05K1/0271 ,  H05K2201/0352 ,  H05K2201/068 ,  H01L2924/00

摘要： An integrated circuit package includes a substrate having a central axis dividing the substrate into an upper half and a lower half and an integrated circuit coupled to the substrate. A layer is provided within the substrate in the lower half thereof that is configured to resist warpage of the integrated circuit package, the layer provided a distance from the central axis.

摘要翻译： 集成电路封装包括具有将基板划分为上半部和下半部的中心轴以及耦合到基板的集成电路的基板。 在其下半部分中的衬底内设置有层，其被配置为抵抗集成电路封装的翘曲，该层与中心轴线设置一段距离。

公开(公告)号：US08629541B2

公开(公告)日：2014-01-14

申请号：US13096618

申请日：2011-04-28

申请人： Min-Shin Ou ,  Chun-Yang Lee ,  Jun Zhai

发明人： Min-Shin Ou ,  Chun-Yang Lee ,  Jun Zhai

IPC分类号： H01L23/02

CPC分类号： H01L23/562 ,  H01L23/3121 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/3511

摘要： A semiconductor structure having a ring. The semiconductor structure includes a substrate, at least one chip, and the ring. The substrate has a first surface. The chip is located on the first surface of the substrate and electrically connected to the substrate. The ring has a first portion and a second portion. In various embodiments, the first and second portions different coefficients of thermal expansion (CTE), and or different cross-sectional widths. In another embodiment, the ring includes a third portion having a CTE different from both the first and second CTEs.

摘要翻译： 具有环的半导体结构。 半导体结构包括衬底，至少一个芯片和环。 衬底具有第一表面。 芯片位于基板的第一表面上并电连接到基板。 环具有第一部分和第二部分。 在各种实施例中，第一和第二部分具有不同的热膨胀系数（CTE）和/或不同的横截面宽度。 在另一个实施例中，环包括具有不同于第一和第二CTE的CTE的第三部分。

公开(公告)号：US08486767B2

公开(公告)日：2013-07-16

申请号：US13166988

申请日：2011-06-23

申请人： Jun Zhai ,  Fei Wang

发明人： Jun Zhai ,  Fei Wang

IPC分类号： H01L21/82

CPC分类号： H01L23/53238 ,  H01L23/528 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure in a semiconductor device may be formed to include a number of segments. Each segment may include a first metal. A barrier structure may be located between the plurality of segments to enable the interconnect structure to avoid electromigration problems.

摘要翻译： 半导体器件中的互连结构可以形成为包括多个段。 每个段可以包括第一金属。 阻挡结构可以位于多个段之间，以使得互连结构能够避免电迁移问题。