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    High order multi-path operational amplifier with output saturation recovery
    1.
    发明授权
    High order multi-path operational amplifier with output saturation recovery 失效
    具有输出饱和恢复功能的高阶多径运算放大器

    公开(公告)号：US06515540B1

    公开(公告)日：2003-02-04

    申请号：US10013559

    申请日：2001-12-10

    申请人： Ammisetti V. Prasad ,  Murari Kejariwal ,  Axel Thomsen

    发明人： Ammisetti V. Prasad ,  Murari Kejariwal ,  Axel Thomsen

    IPC分类号： H03F102

    CPC分类号： H03F3/72 ,  H03F1/086

    摘要： An amplifier is disclosed including multiple integrator stages. The amplifier includes a low-frequency path from a signal input to a signal output and relatively higher-frequency bypass paths around the first integrator stage. The paths converge at a summing node. To prevent instability when the integrators are saturated by large signals, the circuit includes a saturation detector which disables the relatively low-frequency paths during such saturation conditions.

    摘要翻译： 公开了包括多个积分器级的放大器。 放大器包括从信号输入到信号输出的低频路径和围绕第一积分器级的相对较高频率的旁路路径。 路径收敛在求和节点处。 为了防止当积分器被大信号饱和时的不稳定性，该电路包括饱和检测器，其在这种饱和状态期间禁用相对低频路径。

    High order multi-path operational amplifier with reduced input referred offset
    2.
    发明授权
    High order multi-path operational amplifier with reduced input referred offset 有权
    高阶多径运算放大器，具有减少的输入参考偏移

    公开(公告)号：US06466091B1

    公开(公告)日：2002-10-15

    申请号：US09678160

    申请日：2000-10-02

    申请人： Murari Kejariwal ,  Prasad Ammisetti ,  Axel Thomsen

    发明人： Murari Kejariwal ,  Prasad Ammisetti ,  Axel Thomsen

    IPC分类号： H03F368

    CPC分类号： H03F3/45982 ,  H03F1/30 ,  H03F3/343

    摘要： Disclosed in this application is the placement of an additional integrator between the first stage integrator output and the input to the attenuator/low pass filter. This approach reduces the input referred offset by a factor equal to the gain of the additional integrator, and the offset of the additional integrator itself will be divided by the gain of the first-stage integrator.

    摘要翻译： 在本申请中公开了在第一级积分器输出和衰减器/低通滤波器的输入之间放置附加积分器。 该方法将输入参考偏移减少了等于附加积分器的增益的因子，并且附加积分器本身的偏移将除以第一级积分器的增益。

    Non-invasive, low pin count test circuits and methods
    4.
    发明授权
    Non-invasive, low pin count test circuits and methods 有权
    非侵入性，低引脚数测试电路和方法

    公开(公告)号：US07639002B1

    公开(公告)日：2009-12-29

    申请号：US11410362

    申请日：2006-04-25

    申请人： Murari Kejariwal ,  Prisad Ammisetti ,  Axel Thomsen ,  John Laurence Melanson

    发明人： Murari Kejariwal ,  Prisad Ammisetti ,  Axel Thomsen ,  John Laurence Melanson

    IPC分类号： G01R31/28

    CPC分类号： G01R31/31707

    摘要： A method of testing an integrated circuit including a plurality of test nodes includes initiating a test mode and, during a first time interval of the test mode, stepping a level of a supply current of the integrated circuit to a calibration level. Parameters are observed at the plurality of test nodes to detect errors during a second time interval of the test mode and the level of the supply current selectively stepped in response to a number of errors detected. The level of the supply current is decoded to identify the detected errors.

    摘要翻译： 一种测试包括多个测试节点的集成电路的方法包括启动测试模式，并且在测试模式的第一时间间隔期间，使集成电路的电源电平的级别达到校准水平。 在多个测试节点处观察参数以在测试模式的第二时间间隔期间检测错误，并且响应于检测到的错误的数量选择性地步进电源电平。 电源电流的电平被解码以识别检测到的错误。

    Internal node offset voltage test circuits and methods
    6.
    发明授权
    Internal node offset voltage test circuits and methods 有权
    内部节点偏移电压测试电路及方法

    公开(公告)号：US06885211B1

    公开(公告)日：2005-04-26

    申请号：US10117374

    申请日：2002-04-05

    申请人： Axel Thomsen ,  Sherry Wu ,  Murari Kejariwal ,  Ammisetti Prasad ,  John Laurence Melanson

    发明人： Axel Thomsen ,  Sherry Wu ,  Murari Kejariwal ,  Ammisetti Prasad ,  John Laurence Melanson

    IPC分类号： G01R31/28 ,  G01R31/26

    CPC分类号： G01R31/2837

    摘要： A method of testing an integrated circuit includes setting a guardbanded limit for a parameter associated with an embedded node, a deviation from the guardbanded limit under a set of test conditions correlated with a failure of the integrated circuit across a range of operating conditions. A test is performed under the test conditions to detect deviations of the parameter from the guardbanded limit to detect failures of the integrated circuit over the range of operating conditions.

    摘要翻译： 一种测试集成电路的方法包括设置与嵌入式节点相关联的参数的保护限值，与在整个操作条件范围内的集成电路的故障相关的一组测试条件下的保护带限制的偏差。 在测试条件下进行测试，以检测参数与防护带限制的偏差，以检测集成电路在工作条件范围内的故障。

    DUAL LOOP ARCHITECTURE USEFUL FOR A PROGRAMMABLE CLOCK SOURCE AND CLOCK MULTIPLIER APPLICATIONS
    9.
    发明申请
    DUAL LOOP ARCHITECTURE USEFUL FOR A PROGRAMMABLE CLOCK SOURCE AND CLOCK MULTIPLIER APPLICATIONS 有权
    双循环架构可用于可编程时钟源和时钟多路复用器应用

    公开(公告)号：US20090039968A1

    公开(公告)日：2009-02-12

    申请号：US12249457

    申请日：2008-10-10

    申请人： Axel Thomsen ,  Yunteng Huang ,  Jerrell P. Hein

    发明人： Axel Thomsen ,  Yunteng Huang ,  Jerrell P. Hein

    IPC分类号： H03L7/07

    CPC分类号： H03L1/022 ,  H03L1/026 ,  H03L7/095 ,  H03L7/0992 ,  H03L7/1976 ,  H03L7/235 ,  H03L2207/50

    摘要： A first phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal from an oscillator, a controllable oscillator circuit supplying an oscillator output signal, and a multi-modulus feedback divider circuit. A second control loop circuit is selectably coupled through a select circuit to supply a digital control value (M) to the multi-modulus feedback divider circuit of the first loop circuit to thereby control the oscillator output signal. While the second control loop is coupled to supply the control value to the feedback divider circuit, the control value is determined according to a detected difference between the oscillator output signal and a reference signal coupled to the second control loop circuit at a divider circuit. While the second control loop circuit is not coupled to control the first PLL circuit, the first PLL circuit receives a digital control value to control a divide ratio of the feedback divider, the digital control value is determined at least in part according to a stored control value stored in nonvolatile storage, the stored control value corresponding to a desired frequency of the oscillator output signal.

    摘要翻译： 第一锁相环（PLL）电路包括用于从振荡器接收定时参考信号的输入端，提供振荡器输出信号的可控振荡器电路和多模反馈分频器电路。 第二控制回路电路通过选择电路可选地耦合，以将数字控制值（M）提供给第一回路电路的多模反馈分配器电路，从而控制振荡器输出信号。 当第二控制回路被耦合以将控制值提供给反馈分配器电路时，根据在分频器电路处的振荡器输出信号和耦合到第二控制回路电路的参考信号之间的检测到差异来确定控制值。 当第二控制环路电路不耦合以控制第一PLL电路时，第一PLL电路接收数字控制值以控制反馈分频器的分频比，数字控制值至少部分地根据存储的控制 存储在非易失性存储器中的值，所存储的控制值对应于振荡器输出信号的期望频率。

    Dual loop architecture useful for a programmable clock source and clock multiplier applications
    10.
    发明授权
    Dual loop architecture useful for a programmable clock source and clock multiplier applications 有权
    双循环架构可用于可编程时钟源和时钟乘法器应用

    公开(公告)号：US07436227B2

    公开(公告)日：2008-10-14

    申请号：US10878218

    申请日：2004-06-28

    申请人： Axel Thomsen ,  Yunteng Huang ,  Jerrell P. Hein

    发明人： Axel Thomsen ,  Yunteng Huang ,  Jerrell P. Hein

    IPC分类号： H03L7/06

    CPC分类号： H03L1/022 ,  H03L1/026 ,  H03L7/095 ,  H03L7/0992 ,  H03L7/1976 ,  H03L7/235 ,  H03L2207/50

    摘要： A first phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal from an oscillator, a controllable oscillator circuit supplying an oscillator output signal, and a multi-modulus feedback divider circuit. A second control loop circuit is selectably coupled through a select circuit to supply a digital control value (M) to the multi-modulus feedback divider circuit of the first loop circuit to thereby control the oscillator output signal. While the second control loop is coupled to supply the control value to the feedback divider circuit, the control value is determined according to a detected difference between the oscillator output signal and a reference signal coupled to the second control loop circuit at a divider circuit. While the second control loop circuit is not coupled to control the first PLL circuit, the first PLL circuit receives a digital control value to control a divide ratio of the feedback divider, the digital control value is determined at least in part according to a stored control value stored in nonvolatile storage, the stored control value corresponding to a desired frequency of the oscillator output signal.

    摘要翻译： 第一锁相环（PLL）电路包括用于从振荡器接收定时参考信号的输入端，提供振荡器输出信号的可控振荡器电路和多模反馈分频器电路。 第二控制回路电路通过选择电路可选地耦合，以将数字控制值（M）提供给第一回路电路的多模反馈分配器电路，从而控制振荡器输出信号。 当第二控制回路被耦合以将控制值提供给反馈分配器电路时，根据在分频器电路处的振荡器输出信号和耦合到第二控制回路电路的参考信号之间的检测到差异来确定控制值。 当第二控制环路电路不耦合以控制第一PLL电路时，第一PLL电路接收数字控制值以控制反馈分频器的分频比，数字控制值至少部分地根据存储的控制 存储在非易失性存储器中的值，所存储的控制值对应于振荡器输出信号的期望频率。