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1.发明授权公开(公告)号：US06515540B1
公开(公告)日：2003-02-04
申请号：US10013559
申请日：2001-12-10
IPC分类号： H03F102
摘要： An amplifier is disclosed including multiple integrator stages. The amplifier includes a low-frequency path from a signal input to a signal output and relatively higher-frequency bypass paths around the first integrator stage. The paths converge at a summing node. To prevent instability when the integrators are saturated by large signals, the circuit includes a saturation detector which disables the relatively low-frequency paths during such saturation conditions.
摘要翻译： 公开了包括多个积分器级的放大器。 放大器包括从信号输入到信号输出的低频路径和围绕第一积分器级的相对较高频率的旁路路径。 路径收敛在求和节点处。 为了防止当积分器被大信号饱和时的不稳定性，该电路包括饱和检测器，其在这种饱和状态期间禁用相对低频路径。
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2.发明授权Non-invasive, low pin count test circuits and methods utilizing emulated stress conditions 有权非侵入性，低引脚数测试电路和利用模拟应力条件的方法公开(公告)号：US07808263B2
公开(公告)日：2010-10-05
申请号：US12381774
申请日：2009-03-17
IPC分类号： G01R31/02
CPC分类号： G01R31/2884
摘要： An integrated circuit including at least one internal operational block, which includes test control circuitry for initiating a test mode and testing circuitry for verifying an operation of the integrated circuit under a more stringent condition in the test mode as compared to a condition in another operating mode such that proper operation of the integrated circuit is assured in the another operating mode. Pin control circuitry selectively outputs a test signal from a selected pin in the test mode indicative of the operation of the internal block, wherein the selected pin is utilized for exchanging another signal when the integrated circuit is in the another operating mode.
摘要翻译： 一种集成电路，包括至少一个内部操作块，其包括用于启动测试模式的测试控制电路和用于在测试模式中在更严格的条件下验证集成电路的操作的测试电路，与其他操作模式中的条件相比 使得在另一操作模式下确保集成电路的正确操作。 引脚控制电路在指示内部块的操作的测试模式中选择性地输出来自所选引脚的测试信号，其中当集成电路处于另一操作模式时，所选择的引脚用于交换另一信号。
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3.发明授权Non-invasive, low pin count test circuits and methods utilizing emulated stress conditions 有权非侵入性，低引脚数测试电路和利用模拟应力条件的方法公开(公告)号：US07521951B1
公开(公告)日：2009-04-21
申请号：US11402508
申请日：2006-04-12
IPC分类号： G01R31/02
CPC分类号： G01R31/2884
摘要： A method of testing an internal block of an integrated circuit includes initiating a test mode and verifying an operation of the integrated circuit under a more stringent condition in the test mode as compared to a condition in another operating mode such that proper operation of the integrated circuit is assured in the another operating mode. A test signal is selectively output from a selected pin in the test mode indicative of the operation of the internal block, wherein the selected pin is utilized for exchanging another signal when the integrated circuit is in the another operating mode.
摘要翻译： 一种测试集成电路的内部块的方法包括在与其他操作模式中的条件相比较下，在测试模式中在更严格的条件下启动测试模式并验证集成电路的操作，使得集成电路 在另一个操作模式下保证。 在指示内部块的操作的测试模式中，选择性地从所选择的引脚输出测试信号，其中当集成电路处于另一操作模式时，所选择的引脚用于交换另一个信号。
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4.发明申请Non-invasiv, low pin count test circuits and methods utilizing emulated stress conditions 有权非侵入式，低引脚数测试电路和利用模拟应力条件的方法公开(公告)号：US20090179660A1
公开(公告)日：2009-07-16
申请号：US12381774
申请日：2009-03-17
IPC分类号： G01R31/02
CPC分类号： G01R31/2884
摘要： An integrated circuit including at least one internal operational block, which includes test control circuitry for initiating a test mode and testing circuitry for verifying an operation of the integrated circuit under a more stringent condition in the test mode as compared to a condition in another operating mode such that proper operation of the integrated circuit is assured in the another operating mode. Pin control circuitry selectively outputs a test signal from a selected pin in the test mode indicative of the operation of the internal block, wherein the selected pin is utilized for exchanging another signal when the integrated circuit is in the another operating mode.
摘要翻译： 一种集成电路，包括至少一个内部操作块，其包括用于启动测试模式的测试控制电路和用于在测试模式中在更严格的条件下验证集成电路的操作的测试电路，与其他操作模式中的条件相比 使得在另一操作模式下确保集成电路的正确操作。 引脚控制电路在指示内部块的操作的测试模式中选择性地输出来自所选引脚的测试信号，其中当集成电路处于另一操作模式时，所选择的引脚用于交换另一信号。
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公开(公告)号：US08319550B2
公开(公告)日：2012-11-27
申请号：US13008352
申请日：2011-01-18
IPC分类号： H03F1/02
CPC分类号： H03F3/45475 , H03F1/0205 , H03F2203/45514 , H03F2203/45551 , H03G1/0094
摘要： A programmable-gain amplifier has a first input node coupled to receive a first input signal and a control input coupled to receive a gain select signal. The programmable-gain amplifier includes a differential amplifier having a first input and a first output and a plurality of capacitors. A first terminal of each of the plurality of capacitors is coupled to the first input of the differential amplifier, and a second terminal of each of the plurality of capacitors is coupled to the first input node during a sampling phase of the programmable-gain amplifier and selectively coupled to the first output of the differential amplifier, based on the gain select signal, during a gain phase of the programmable-gain amplifier.
摘要翻译： 可编程增益放大器具有耦合以接收第一输入信号的第一输入节点和耦合以接收增益选择信号的控制输入。 可编程增益放大器包括具有第一输入和第一输出以及多个电容的差分放大器。 多个电容器中的每一个的第一端子耦合到差分放大器的第一输入端，并且多个电容器中的每一个的第二端子在可编程增益放大器的采样阶段期间耦合到第一输入节点，并且 在可编程增益放大器的增益阶段期间，基于增益选择信号选择性地耦合到差分放大器的第一输出。
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公开(公告)号：US08026760B1
公开(公告)日：2011-09-27
申请号：US12846475
申请日：2010-07-29
申请人： Ammisetti V. Prasad
发明人： Ammisetti V. Prasad
IPC分类号： H03F1/02
CPC分类号： H03F3/45475 , H03F3/005 , H03F2200/411 , H03F2203/45512 , H03F2203/45514 , H03F2203/45534 , H03F2203/45544 , H03F2203/45551 , H03F2203/45582 , H03F2203/45616 , H03F2203/45631 , H03F2203/45644 , H03F2203/45724 , H03F2203/45726
摘要： A switched capacitor circuit utilizes a pair of serially connected differential amplifiers that have plus inputs, minus inputs, plus outputs, and minus outputs. Feedback to the plus/minus inputs is in a first configuration relative to the output of the pair of differential amplifiers in a sampling mode and a second configuration in a hold mode. Similarly, the plus/minus inputs relative to the plus/minus outputs of the serially connected differential amplifiers is reversed between the sampling and hold modes.
摘要翻译： 开关电容电路使用一对串联的差分放大器，它们具有正输入，减输入，加输出和负输出。 相对于正/负输入的反馈是相对于采样模式中的一对差分放大器的输出和处于保持模式的第二配置的第一配置。 类似地，相对于串联差分放大器的正/负输出的正/负输入在采样和保持模式之间相反。
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公开(公告)号：US08643526B1
公开(公告)日：2014-02-04
申请号：US13779751
申请日：2013-02-28
IPC分类号： H03M1/12
CPC分类号： H03M1/0663 , H03F3/387 , H03F3/45475 , H03M1/12
摘要： A data acquisition system for converting an analog input signal to a digital output signal includes a programmable gain amplifier (PGA), an analog to digital converter (ADC), and an averaging module. The PGA generates first and second amplified signals during respective first and second conversion cycles. The first and second amplified signals include respective first and second amplified input signals and first and second sets of offset and noise signals. The first and second amplified input signals have the same polarities, and the first and second sets of offset and noise signals have opposite polarities. The ADC generates first and second digital samples corresponding to the first and second amplified signals respectively and the averaging module averages the first and second digital samples to eliminate the first and second sets of offset and noise signals from the digital output signal.
摘要翻译： 用于将模拟输入信号转换为数字输出信号的数据采集系统包括可编程增益放大器（PGA），模数转换器（ADC）和平均模块。 PGA在相应的第一和第二转换周期期间产生第一和第二放大信号。 第一和第二放大信号包括相应的第一和第二放大输入信号以及第一和第二组偏移和噪声信号。 第一和第二放大的输入信号具有相同的极性，并且第一和第二组偏移和噪声信号具有相反的极性。 ADC分别产生对应于第一和第二放大信号的第一和第二数字采样，并且平均模块对第一和第二数字采样进行平均以消除来自数字输出信号的第一和第二组偏移和噪声信号。
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公开(公告)号：US20120182067A1
公开(公告)日：2012-07-19
申请号：US13008352
申请日：2011-01-18
CPC分类号： H03F3/45475 , H03F1/0205 , H03F2203/45514 , H03F2203/45551 , H03G1/0094
摘要： A programmable-gain amplifier has a first input node coupled to receive a first input signal and a control input coupled to receive a gain select signal. The programmable-gain amplifier includes a differential amplifier having a first input and a first output and a plurality of capacitors. A first terminal of each of the plurality of capacitors is coupled to the first input of the differential amplifier, and a second terminal of each of the plurality of capacitors is coupled to the first input node during a sampling phase of the programmable-gain amplifier and selectively coupled to the first output of the differential amplifier, based on the gain select signal, during a gain phase of the programmable-gain amplifier.
摘要翻译： 可编程增益放大器具有耦合以接收第一输入信号的第一输入节点和耦合以接收增益选择信号的控制输入。 可编程增益放大器包括具有第一输入和第一输出以及多个电容的差分放大器。 多个电容器中的每一个的第一端子耦合到差分放大器的第一输入端，并且多个电容器中的每一个的第二端子在可编程增益放大器的采样阶段期间耦合到第一输入节点，并且 在可编程增益放大器的增益阶段期间，基于增益选择信号选择性地耦合到差分放大器的第一输出。
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9.发明申请公开(公告)号：US20080174372A1
公开(公告)日：2008-07-24
申请号：US11694348
申请日：2007-03-30
IPC分类号： H03F3/68
CPC分类号： H03F1/0222 , H03F3/187 , H03F3/45183 , H03F3/45475 , H03F2200/03 , H03F2200/351 , H03F2200/405 , H03F2200/408 , H03F2200/504 , H03F2200/516 , H03F2203/45138
摘要： A signal processing system and method utilizes a multi-stage amplifier to amplify an input signal. The multi-stage amplifier uses a mixed set of voltage rails to improve the operating efficiency of at least one of the amplification stages while allowing other amplification stages to operate in a predetermined operating mode. Efficiency of at least one of the stages is improved by supplying at least one variable voltage rail to an amplification stage of the multi-stage amplifier. The variable voltage rail varies in response to changes in an input signal voltage to the amplification stage. Accordingly, at least one amplification stage utilizes a variable voltage rail, and all amplification stages are supplied with a set of voltage rails that provides sufficient input signal headroom, thus, providing amplification stage efficiency and adequate voltage to allow operation of all amplification stages.
摘要翻译： 信号处理系统和方法利用多级放大器放大输入信号。 多级放大器使用混合的电压轨，以提高至少一个放大级的工作效率，同时允许其它放大级在预定的工作模式下工作。 通过向多级放大器的放大级提供至少一个可变电压轨来提高至少一个级的效率。 可变电压轨响应于到放大级的输入信号电压的变化而变化。 因此，至少一个放大级利用可变电压轨，并且所有放大级被提供有提供足够的输入信号余量的一组电压轨，从而提供放大级效率和足够的电压以允许所有放大级的操作。
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公开(公告)号：US6133769A
公开(公告)日：2000-10-17
申请号：US201081
申请日：1998-11-30
CPC分类号： H03L7/18 , H03L7/0891 , H03L7/095
摘要： A phase locked loop comprises a phase locking circuit (16) which includes a phase/frequency detector (18) capable of outputting up and down signals to a charge pump (22) through separate signal paths (24, 26) and a phase lock detector (34) coupled to receive the up and down signals. The phase lock detector (34) determines the difference between the up and down signals from the phase/frequency detector (18) and in response generates a phase lock indicator signal PLL.sub.-- OUT.
摘要翻译： 锁相环包括相位锁定电路（16），该锁相电路包括能够通过分离的信号路径（24,26）向电荷泵（22）输出上下信号的相位/频率检测器（18）和相位锁定检测器 （34），用于接收上下信号。 相位锁定检测器（34）确定来自相位/频率检测器（18）的上升和下降信号之间的差异，并且响应产生锁相指示器信号PLL-OUT。
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