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    Autonomous initialization of non-volatile random access memory in a computer system
    2.
    发明授权
    Autonomous initialization of non-volatile random access memory in a computer system 有权
    计算机系统中非易失性随机存取存储器的自动初始化

    公开(公告)号：US09378133B2

    公开(公告)日：2016-06-28

    申请号：US13997945

    申请日：2011-09-30

    申请人： Murugasamy K. Nachimuthu ,  Mohan Kumar ,  Dimitrios Ziakas

    发明人： Murugasamy K. Nachimuthu ,  Mohan Kumar ,  Dimitrios Ziakas

    IPC分类号： G06F12/02 ,  G06F9/44

    CPC分类号： G06F12/0246 ,  G06F9/4403

    摘要： A non-volatile random access memory (NVRAM) is used in a computer system to store information that allows the NVRAM to autonomously initialize itself at power-on. The computer system includes a processor, an NVRAM controller coupled to the processor, and an NVRAM that comprises the NVRAM controller. The NVRAM is byte-rewritable and byte-erasable by the processor. The NVRAM stores a memory interface table containing information for the NVRAM controller to autonomously initialize the NVRAM upon power-on of the computer system without interacting with the processor and firmware outside of the NVRAM. The information is provided by the NVRAM controller to the processor to allow the processor to access the NVRAM.

    摘要翻译： 在计算机系统中使用非易失性随机存取存储器（NVRAM）来存储允许NVRAM在上电时自动初始化的信息。 计算机系统包括处理器，耦合到处理器的NVRAM控制器和包括NVRAM控制器的NVRAM。 NVRAM是字节可重写的，可由处理器字节擦除。 NVRAM存储包含NVRAM控制器的信息的存储器接口表，用于在计算机系统上电时自动初始化NVRAM，而不与NVRAM之外的处理器和固件交互。 该信息由NVRAM控制器提供给处理器，以允许处理器访问NVRAM。

    AUTONOMOUS INITIALIZATION OF NON-VOLATILE RANDOM ACCESS MEMORY IN A COMPUTER SYSTEM
    3.
    发明申请
    AUTONOMOUS INITIALIZATION OF NON-VOLATILE RANDOM ACCESS MEMORY IN A COMPUTER SYSTEM 有权
    计算机系统中非易失性随机存取存储器的自动初始化

    公开(公告)号：US20130304980A1

    公开(公告)日：2013-11-14

    申请号：US13997945

    申请日：2011-09-30

    申请人： Murugasamy K. Nachimuthu ,  Mohan Kumar ,  Dimitrios Ziakas

    发明人： Murugasamy K. Nachimuthu ,  Mohan Kumar ,  Dimitrios Ziakas

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0246 ,  G06F9/4403

    摘要： A non-volatile random access memory (NVRAM) is used in a computer system to store information that allows the NVRAM to autonomously initialize itself at power-on. The computer system includes a processor, an NVRAM controller coupled to the processor, and an NVRAM that comprises the NVRAM controller. The NVRAM is byte-rewritable and byte-erasable by the processor. The NVRAM stores a memory interface table containing information for the NVRAM controller to autonomously initialize the NVRAM upon power-on of the computer system without interacting with the processor and firmware outside of the NVRAM. The information is provided by the NVRAM controller to the processor to allow the processor to access the NVRAM.

    摘要翻译： 在计算机系统中使用非易失性随机存取存储器（NVRAM）来存储允许NVRAM在上电时自动初始化的信息。 计算机系统包括处理器，耦合到处理器的NVRAM控制器和包括NVRAM控制器的NVRAM。 NVRAM是字节可重写的，可由处理器字节擦除。 NVRAM存储包含NVRAM控制器的信息的存储器接口表，用于在计算机系统上电时自动初始化NVRAM，而不与NVRAM之外的处理器和固件交互。 该信息由NVRAM控制器提供给处理器，以允许处理器访问NVRAM。

    Techniques for Handling Errors in Persistent Memory
    6.
    发明申请
    Techniques for Handling Errors in Persistent Memory 有权
    在持久记忆中处理错误的技术

    公开(公告)号：US20150378808A1

    公开(公告)日：2015-12-31

    申请号：US14319387

    申请日：2014-06-30

    申请人： Mohan J. Kumar ,  Murugasamy K. Nachimuthu ,  Camille C. Raad

    发明人： Mohan J. Kumar ,  Murugasamy K. Nachimuthu ,  Camille C. Raad

    IPC分类号： G06F11/07

    CPC分类号： G06F11/073 ,  G06F11/0769 ,  G06F11/0787 ,  G09C1/00 ,  G11C5/04 ,  G11C29/52 ,  G11C2029/0409

    摘要： Examples may include a basic input/output system (BIOS) for a computing platform communicating with a controller for a non-volatile dual in-line memory module (NVDIMM). Communication between the BIOS and the controller may include a request for the controller to scan and identify error locations in non-volatile memory at the NVDIMM. The non-volatile memory may be capable of providing persistent memory for the NVDIMM.

    摘要翻译： 示例可以包括用于与用于非易失性双列直插式存储器模块（NVDIMM）的控制器通信的计算平台的基本输入/输出系统（BIOS）。 BIOS和控制器之间的通信可以包括控制器在NVDIMM下扫描和识别非易失性存储器中的错误位置的请求。 非易失性存储器可能能够为NVDIMM提供持久存储器。

    ENHANCED SYSTEM SLEEP STATE SUPPORT IN SERVERS USING NON-VOLATILE RANDOM ACCESS MEMORY
    7.
    发明申请
    ENHANCED SYSTEM SLEEP STATE SUPPORT IN SERVERS USING NON-VOLATILE RANDOM ACCESS MEMORY 有权
    使用非易失性随机访问存储器的服务器中的增强系统休眠状态支持

    公开(公告)号：US20130290759A1

    公开(公告)日：2013-10-31

    申请号：US13976901

    申请日：2011-12-13

    申请人： Mohan J. Kumar ,  Murugasamy K. Nachimuthu

    发明人： Mohan J. Kumar ,  Murugasamy K. Nachimuthu

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3206 ,  G06F1/3275 ,  G06F1/3287 ,  G06F9/4418 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D50/20

    摘要： A non-volatile random access memory (NVRAM) is used in a computer system to enhance support to sleep states. The computer system includes a processor, a non-volatile random access memory (NVRAM) that is byte-rewritable and byte-erasable, and power management (PM) module. A dynamic random access memory (DRAM) provides a portion of system address space. The PM module intercepts a request initiated by an operating system for entry into a sleep state, copies data from the DRAM to the NVRAM, maps the portion of the system address space from the DRAM to the NVRAM, and turns off the DRAM when transitioning into the sleep state. Upon occurrence of a wake event, the PM module returns control to the operating system such that the computer system resumes working state operations without the operating system knowing that the portion of the system address space has been mapped to the NVRAM.

    摘要翻译： 在计算机系统中使用非易失性随机存取存储器（NVRAM）来增强对睡眠状态的支持。 计算机系统包括处理器，可字节可重写和字节可擦除的非易失性随机存取存储器（NVRAM）和电源管理（PM）模块。 动态随机存取存储器（DRAM）提供系统地址空间的一部分。 PM模块拦截由操作系统启动进入休眠状态的请求，将数据从DRAM复制到NVRAM，将系统地址空间的一部分映射到NVRAM，并将DRAM转换为 睡眠状态。 在发生唤醒事件时，PM模块向操作系统返回控制，使得计算机系统恢复工作状态操作，而操作系统不知道系统地址空间的一部分已经映射到NVRAM。

    MECHANISM FOR EFFICIENT DISCOVERY OF STORAGE RESOURCES IN A RACK SCALE ARCHITECTURE SYSTEM
    9.
    发明申请
    MECHANISM FOR EFFICIENT DISCOVERY OF STORAGE RESOURCES IN A RACK SCALE ARCHITECTURE SYSTEM 审中-公开

    公开(公告)号：US20180034909A1

    公开(公告)日：2018-02-01

    申请号：US15221707

    申请日：2016-07-28

    申请人： Murugasamy K. Nachimuthu ,  Mohan J. Kumar

    发明人： Murugasamy K. Nachimuthu ,  Mohan J. Kumar

    IPC分类号： H04L29/08 ,  H04L12/24

    摘要： Mechanisms for efficient discovery of storage resources in a Rack Scale Architecture (RSA) system and associated methods, apparatus, and systems. A rack is populated with pooled system drawers including pooled compute drawers and pooled storage drawers communicatively coupled via input-output (IO) cables. Compute nodes including one or more processors, memory resources, and optional local storage resources are installed in the pooled compute drawers, and are enabled to be selectively-coupled to storage resources in the pooled storage drawers over virtual attachment links. During a discovery process, a compute node determines storage resource characteristics of storage resources it may be selectively-coupled to and the attachment links used to access the storage resources. The storage resource characteristics are aggregated by a pod manager that uses corresponding configuration information to dynamically compose compute nodes for rack users based on user needs.

    Machine check summary register
    10.
    发明授权
    Machine check summary register 有权
    机器检查摘要寄存器

    公开(公告)号：US09317360B2

    公开(公告)日：2016-04-19

    申请号：US13995458

    申请日：2011-12-29

    申请人： Jose A. Vargas ,  Mohan J. Kumar ,  James B. Crossland ,  Murugasamy K. Nachimuthu ,  Theodros Yigzaw

    发明人： Jose A. Vargas ,  Mohan J. Kumar ,  James B. Crossland ,  Murugasamy K. Nachimuthu ,  Theodros Yigzaw

    IPC分类号： G06F11/00 ,  G06F11/08 ,  G06F11/22 ,  G06F11/10 ,  G06F11/07

    CPC分类号： G06F11/1004 ,  G06F11/0724 ,  G06F11/0793

    摘要： In some implementations, a processor may include a machine check architecture having a plurality of error reporting registers able to receive data for machine check errors. A summary register may include a plurality of settable locations that each represents at least one of the error reporting registers. One or more of the settable locations in the summary register may be set to indicate whether one or more of the error reporting registers maintain data for a machine check error. Accordingly, when a machine check error occurs, the summary register may be accessed to identify if any error reporting registers in a processor's view contain valid error data, rather than having to read each of the error reporting registers in the processor's view.

    摘要翻译： 在一些实现中，处理器可以包括具有多个错误报告寄存器的机器检查架构，其能够接收用于机器检查错误的数据。 总结寄存器可以包括多个可设置位置，每个位置可以代表错误报告寄存器中的至少一个。 可以将汇总寄存器中的一个或多个可设置位置设置为指示一个或多个错误报告寄存器是否保持机器检查错误的数据。 因此，当发生机器检查错误时，可以访问总结寄存器以识别处理器视图中的任何错误报告寄存器是否包含有效的错误数据，而不是在处理器视图中读取每个错误报告寄存器。