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1.发明授权Vertical insulated gate semiconductor device with less influence from the parasitic bipolar effect 失效垂直绝缘栅极半导体器件，具有较小的寄生双极效应影响
公开(公告)号：US5285094A
公开(公告)日：1994-02-08
申请号：US921226
申请日：1992-07-29
IPC分类号： H01L21/225 , H01L21/331 , H01L21/336 , H01L29/739 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/66333 , H01L21/2257 , H01L29/66712 , H01L29/7395 , H01L29/7802
摘要： The present invention relates to a semiconductor device having an n-type semiconductor region forming one of the main surfaces of a semiconductor substrate, with a plurality of p-type semiconductor regions formed in the n-type semiconductor region. Two exposed n-type semiconductor regions are formed on each of the p-type semiconductor regions, with a main electrode formed on the n-type semiconductor regions and the exposed p-type semiconductor region therebetween. An insulated gate extends from one of the n-type semiconductor regions in one of the p-type semiconductor regions to a closer one of the n-type semiconductor regions in an adjacent p-type semiconductor region. The length of the insulated gate is longer than a distance between adjacent insulated gates.
摘要翻译： 本发明涉及一种半导体器件，其具有形成半导体衬底的主表面之一的n型半导体区域，其中形成在n型半导体区域中的多个p型半导体区域。 在p型半导体区域的每一个上形成有两个暴露的n型半导体区域，其中主电极形成在n型半导体区域上，并且其间暴露的p型半导体区域。 绝缘栅极从p型半导体区域中的一个中的n型半导体区域中的一个延伸到相邻p型半导体区域中的更靠近的n型半导体区域中的一个。 绝缘栅极的长度大于相邻绝缘栅之间的距离。
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公开(公告)号：US5179034A
公开(公告)日：1993-01-12
申请号：US683695
申请日：1991-04-11
IPC分类号： H01L21/225 , H01L21/331 , H01L21/336 , H01L29/739 , H01L29/78
CPC分类号： H01L29/66333 , H01L21/2257 , H01L29/66712 , H01L29/7395 , H01L29/7802 , Y10S148/126
摘要： A method for fabricating an insulated gate semiconductor device comprises the steps of forming insulated gates on an n.sup.- -layer surface, forming p-well layers in the n.sup.- -layer using the insulated gates as masks, forming phosphosilicate glass layers on the side walls of the insulated gates and diffusing the impurities from the phosphosilicate glass layers into the p-well layers to form n.sup.30 -source layer.
摘要翻译： 一种用于制造绝缘栅半导体器件的方法包括以下步骤：在n层表面上形成绝缘栅极，使用绝缘浇口作为掩模在n层中形成p阱层，在侧壁上形成磷硅玻璃层 的绝缘栅极，并将杂质从磷硅玻璃层扩散到p阱层中以形成n30源层。
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公开(公告)号：US5032532A
公开(公告)日：1991-07-16
申请号：US233007
申请日：1988-08-17
IPC分类号： H01L29/68 , H01L21/225 , H01L21/331 , H01L21/336 , H01L29/739 , H01L29/78
CPC分类号： H01L29/66333 , H01L21/2257 , H01L29/66712 , H01L29/7395 , H01L29/7802 , Y10S148/126
摘要： A method for fabricating an insulated gate semiconductor device comprises the steps of forming insulated gates on an n.sup.- -layer surface, forming p-well layers in the n.sup.- -layer using the insulated gates as masks, forming phosphosilicate glass layers on the side walls of the insulated gates and diffusing the impurities from the phosphosilicate glass layers into the p-well layers to form n.sup.+ -source layer.
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4.发明授权Vertical insulated gate semiconductor device having high current density and high reliability 失效具有高电流密度和高可靠性的垂直绝缘栅半导体器件
公开(公告)号：US5670811A
公开(公告)日：1997-09-23
申请号：US430289
申请日：1995-04-28
IPC分类号： H01L21/225 , H01L21/331 , H01L21/336 , H01L29/739 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/66333 , H01L21/2257 , H01L29/66712 , H01L29/7395 , H01L29/7802
摘要： The present invention is directed to a semiconductor device which can achieve high current density and which has a high reliability. In the insulated gate semiconductor device according to the present invention, a plurality of insulating gates are provided, with each two adjacent insulating gates being spaced from each other, the insulating gates being provided on a second semiconductor region of a first conductivity type. A first semiconductor region, of the same or different conductivity type from that of the second semiconductor region, extends from a surface of the second semiconductor region opposed to the surface thereof having the insulating gates thereon. A plurality of third semiconductor regions are provided in the second semiconductor region, between the insulating gates and aligned therewith, and two fourth semiconductor regions are provided extending into each of the third semiconductor regions, aligned with the sides of adjacent insulating gates. Electrodes are respectively provided in contact with the first semiconductor region and in contact with the third and fourth semiconductor regions, the electrode in contact with the third and fourth semiconductor regions contacting such regions in the space between adjacent insulating gates. By utilizing such aligned third and fourth semiconductor regions, an insulated gate semiconductor device which operates at high current densities can be fabricated at high accuracy, and such device will be less influenced by parasitic bipolar transistor effects.
摘要翻译： 本发明涉及能够实现高电流密度并且具有高可靠性的半导体器件。 在根据本发明的绝缘栅半导体器件中，设置有多个绝缘栅极，每个两个相邻的绝缘栅极彼此间隔开，绝缘栅极设置在第一导电类型的第二半导体区域上。 与第二半导体区域相同或不同的导电类型的第一半导体区域从与其上具有绝缘栅极的表面相对的第二半导体区域的表面延伸。 多个第三半导体区域设置在第二半导体区域中，在绝缘栅极之间并与其对准，并且提供两个第四半导体区域，其延伸到每个第三半导体区域中，与相邻绝缘栅极的侧面对准。 电极分别设置成与第一半导体区域接触并且与第三和第四半导体区域接触，与第三和第四半导体区域接触的电极与相邻绝缘栅极之间的空间中的这些区域接触。 通过利用这种对准的第三和第四半导体区域，可以以高精度制造以高电流密度工作的绝缘栅极半导体器件，并且这种器件将受寄生双极晶体管效应的影响较小。
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公开(公告)号：US5804868A
公开(公告)日：1998-09-08
申请号：US600459
申请日：1996-02-13
IPC分类号： H01L29/78 , H01L21/331 , H01L21/8222 , H01L27/06 , H01L29/06 , H01L29/40 , H01L29/73 , H01L29/732 , H01L29/74 , H01L29/861 , H02P27/06 , H01L23/58
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/404 , H01L29/408 , H02P27/06 , H01L2924/0002
摘要： A highly reliable semiconductor device having a planar junction, which comprises a main junction and a plurality of field limiting ring regions surrounding the main junction, and an electrically floating conductive layer to completely cover that part of the surface of an n.sup.- layer between the main junction and the nearest field limiting ring region thereto through an insulating layer to suppress influences by external factors such as charged particles, etc. In accordance with such a structured device, when a voltage for making the main junction into a reverse bias state is applied, the potential of the conductive layer becomes fixed to an intermediate potential between the main junction and the nearest field limiting ring region thereto and plays a role of shield effect. In fact, even if the device is incorporated into a resin-sealed package and subjected to reliability tests (high temperature DC reverse bias tests), the breakdown voltage is not changed at all. Also, rather than effecting a device in which the conductive layer is electrically floating, the conductive layer which covers an overlying area between the main junction and the nearest field limiting ring region thereto can be electrically connected to the nearest field limiting ring.
摘要翻译： 具有平面结的高度可靠的半导体器件，其包括主结和围绕主结的多个场限制环区域，以及电浮动导电层，以完全覆盖主层之间的n层表面的那部分 并且通过绝缘层向其最近的限界环区域，以抑制外部因素如带电粒子等的影响。根据这种结构化器件，当施加用于使主结点成为反向偏置状态的电压时， 导电层的电位固定在主结点与其最近的限界环区之间的中间电位，起到屏蔽作用。 事实上，即使将该器件并入树脂密封封装并进行可靠性测试（高温直流反向偏压测试），也完全不会发生击穿电压的变化。 此外，不是实现其中导电层电浮置的器件，覆盖主结和其最近的限界环区之间的覆盖区域的导电层可以电连接到最近的场限制环。
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公开(公告)号：US5208471A
公开(公告)日：1993-05-04
申请号：US762793
申请日：1991-09-19
IPC分类号： H01L21/331 , H01L21/336 , H01L29/06 , H01L29/10 , H01L29/739 , H01L29/78
CPC分类号： H01L29/66719 , H01L29/1095 , H01L29/41741 , H01L29/66333 , H01L29/66712 , H01L29/7395 , H01L29/7811 , H01L29/0696
摘要： A semiconductor device comprises a semiconductor substrate, a semiconductor layer of a first conductivity type formed on said semiconductor substrate, a first semiconductor well region of a second conductivity type and second semiconductor well regions of the second conductivity type, the latter two types of regions being formed in said semiconductor layer. The first semiconductor well region is located at the peripheral area of the semiconductor, and the well is deeper than the well of the second semiconductor well regions. Third semiconductor well regions of the first conductivity type are formed in the second semiconductor well regions. Gate electrodes and an emitter (source) electrode are formed at specified positions on the upper surface of the semiconductor device, and a collector (drain) electrode is formed on the bottom surface.
摘要翻译： 半导体器件包括半导体衬底，形成在所述半导体衬底上的第一导电类型的半导体层，第二导电类型的第一半导体阱区域和第二导电类型的第二半导体阱区域，后两个区域是 形成在所述半导体层中。 第一半导体阱区位于半导体的周边区域，阱比第二半导体阱区的阱深。 第一导电类型的第三半导体阱区形成在第二半导体阱区中。 在半导体器件的上表面上的特定位置处形成栅电极和发射极（源极），在底面形成集电极（漏极）电极。
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7.发明授权Method of manufacturing a power semiconductor device using implants and solid diffusion source 失效使用植入物和固体扩散源制造功率半导体器件的方法
公开(公告)号：US5262339A
公开(公告)日：1993-11-16
申请号：US17420
申请日：1993-02-10
IPC分类号： H01L21/331 , H01L21/336 , H01L29/06 , H01L29/10 , H01L29/739 , H01L29/78 , H01L21/266
CPC分类号： H01L29/66333 , H01L29/1095 , H01L29/66712 , H01L29/7395 , H01L29/7802 , H01L29/0696 , Y10S148/126
摘要： A semiconductor device comprises a semiconductor substrate, a semiconductor layer of a first conductivity type formed on said semiconductor substrate, a first semiconductor well region of a second conductivity type and second semiconductor well regions of the second conductivity type, the latter two types of regions being formed in said semiconductor layer. The first semiconductor well region is located at the peripheral area of the semiconductor, and the well is deeper than the well of the second semiconductor well regions. Third semiconductor well regions of the first conductivity type are formed in the second semiconductor well regions. Gate electrodes and an emitter (source) electrode are formed at specified positions on the upper surface of the semiconductor device, and a collector (drain) electrode is formed on the bottom surface.
摘要翻译： 半导体器件包括半导体衬底，形成在所述半导体衬底上的第一导电类型的半导体层，第二导电类型的第一半导体阱区域和第二导电类型的第二半导体阱区域，后两个区域是 形成在所述半导体层中。 第一半导体阱区位于半导体的周边区域，阱比第二半导体阱区的阱深。 第一导电类型的第三半导体阱区形成在第二半导体阱区中。 在半导体器件的上表面上的特定位置处形成栅电极和发射极（源极），在底面形成集电极（漏极）电极。
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公开(公告)号：US06614190B2
公开(公告)日：2003-09-02
申请号：US09939749
申请日：2001-08-28
申请人： Hiroyuki Tomita , Kazuo Mera , Isao Hashimoto , Yasunori Nakano , Takayoshi Seki
发明人： Hiroyuki Tomita , Kazuo Mera , Isao Hashimoto , Yasunori Nakano , Takayoshi Seki
IPC分类号： H05B3126
CPC分类号： H01J37/3171 , H01J2237/20 , H01L21/68707
摘要： A wafer holder for holding a wafer includes a wafer holder base, a wafer fixing part, holder pins, a bearing, a housing, and a coil spring. The wafer fixing part is fixed to an outer circumference of a wafer holder. The holder pins are arranged to face the wafer fixing part. The holder pin is rotatably supported by the bearing. The holder pins are movably supported along the diameter direction of the wafer holder base by the coil spring. In the process of holding a side of the wafer with the holder pins, when force from the wafer works on the holder pins, the holder pins are rotated with a Z axis as a center, thus reducing frictional force between the holder pin and the wafer. Accordingly, it is possible to prevent particle generation from holding an implanting object.
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