公开(公告)号：US20060006903A1

公开(公告)日：2006-01-12

申请号：US11175634

申请日：2005-07-05

申请人： Myung-Hun Choi ,  Nam-Seog Kim ,  Chul-Sung Park

发明人： Myung-Hun Choi ,  Nam-Seog Kim ,  Chul-Sung Park

IPC分类号： H03K19/003

CPC分类号： H04L25/0278 ,  H03K19/0005

摘要： A programmable impedance controller and a method of operating prevent or substantially reduce internal noise and an influence from external noise lasting for a long time. The programmable impedance controller for comparing a pad voltage of a pad connected to an external determination impedance with a reference voltage, and for outputting an impedance control signal, and for performing a digital coding to an impedance code corresponding to the impedance control signal, includes a clock controller and a counter. The clock controller outputs a first clock signal in a reset mode and outputs a second clock signal in an operating mode, in response to an applied clock signal. The counter sequentially updates code data, one code step per clock period, in response to the first clock signal in the reset mode, and outputs update code data. In an operating mode, the counter outputs the update code data updated in the reset mode in response to the second clock signal.

摘要翻译： 可编程阻抗控制器和操作方法可以防止或显着降低内部噪声以及长时间持续的外部噪声的影响。 可编程阻抗控制器，用于将连接到外部确定阻抗的焊盘的焊盘电压与参考电压进行比较，并用于输出阻抗控制信号，以及对与阻抗控制信号相对应的阻抗代码执行数字编码，包括： 时钟控制器和计数器。 时钟控制器以复位模式输出第一时钟信号，并且响应于所施加的时钟信号而在操作模式下输出第二时钟信号。 响应于复位模式中的第一时钟信号，计数器依次更新代码数据，每时钟周期的一个代码步长，并输出更新代码数据。 在操作模式中，计数器响应于第二时钟信号输出以复位模式更新的更新代码数据。

公开(公告)号：US07288966B2

公开(公告)日：2007-10-30

申请号：US11175634

申请日：2005-07-05

申请人： Myung-Han Choi ,  Nam-Seog Kim ,  Chul-Sung Park

发明人： Myung-Han Choi ,  Nam-Seog Kim ,  Chul-Sung Park

IPC分类号： H03K19/0175

CPC分类号： H04L25/0278 ,  H03K19/0005

摘要： A programmable impedance controller and a method of operating to prevent or substantially reduce internal noise and an influence from external noise lasting for a long time. The programmable impedance controller for comparing a pad voltage of a pad connected to an external determination impedance with a reference voltage, and for outputting an impedance control signal, and for performing a digital coding to an impedance code corresponding to the impedance control signal, includes a clock controller and a counter. The clock controller outputs a first clock signal in a reset mode and outputs a second clock signal in an operating mode, in response to an applied clock signal. The counter sequentially updates code data, one code step per clock period, in response to the first clock signal in the reset mode, and outputs update code data. In an operating mode, the counter outputs the update code data updated in the reset mode in response to the second clock signal.

摘要翻译： 一种可编程阻抗控制器和一种操作方法，用于防止或大幅度地减少内部噪声以及长时间持续的外部噪声的影响。 可编程阻抗控制器，用于将连接到外部确定阻抗的焊盘的焊盘电压与参考电压进行比较，并用于输出阻抗控制信号，以及对与阻抗控制信号相对应的阻抗代码执行数字编码，包括： 时钟控制器和计数器。 时钟控制器以复位模式输出第一时钟信号，并且响应于所施加的时钟信号而在操作模式下输出第二时钟信号。 响应于复位模式中的第一时钟信号，计数器依次更新代码数据，每时钟周期的一个代码步长，并输出更新代码数据。 在操作模式中，计数器响应于第二时钟信号输出以复位模式更新的更新代码数据。

公开(公告)号：US07548485B2

公开(公告)日：2009-06-16

申请号：US11845191

申请日：2007-08-27

申请人： Young-Seung Kim ,  Chul-Sung Park

发明人： Young-Seung Kim ,  Chul-Sung Park

IPC分类号： G11C8/02

CPC分类号： G11C11/413

摘要： A semiconductor memory device capable of synchronous/asynchronous operation and data input/output method thereof are provided. The semiconductor memory device includes a memory cell array, a peripheral circuit configured to write data to a cell in the memory cell array and to read data from the cell, and a bypass control unit configured to control a late write operation and a bypass operation of the peripheral circuit according to mode conversion of the semiconductor memory device. Accordingly, data coherency can be maintained. In addition, dummy cycle time that may occur during the mode conversion can be prevented by generating a mode conversion signal only in response to toggling of a clock signal.

摘要翻译： 提供能够进行同步/异步操作的半导体存储器件及其数据输入/输出方法。 半导体存储器件包括存储单元阵列，外围电路，被配置为向存储单元阵列中的单元写入数据并从单元读取数据;以及旁路控制单元，被配置为控制延迟写入操作和旁路操作 外围电路根据半导体存储器件的模式转换。 因此，可以保持数据一致性。 此外，可以通过仅响应于时钟信号的切换而产生模式转换信号来防止在模式转换期间可能发生的伪周期时间。

公开(公告)号：US06958947B2

公开(公告)日：2005-10-25

申请号：US10359075

申请日：2003-02-06

申请人： Chul-Sung Park ,  Hyang-Ja Yang ,  Seung-Min Lee ,  Yong-Hwan Noh

发明人： Chul-Sung Park ,  Hyang-Ja Yang ,  Seung-Min Lee ,  Yong-Hwan Noh

IPC分类号： G11C5/14 ,  G11C29/12 ,  G11C29/50

CPC分类号： G11C29/12005 ,  G11C5/147 ,  G11C11/41 ,  G11C29/12 ,  G11C29/50 ,  G11C2207/2254

摘要： A semiconductor memory device which includes an internal voltage generator circuit for adjusting an external power supply voltage and generating first and second internal power supply voltages. The first internal power supply voltage is supplied to a memory cell array via a first power supply line, and the second internal power supply voltage is supplied to a peripheral circuit via a second power supply line. A control circuit controls the internal voltage generator circuit so that the levels of the first and second internal power supply voltages vary depending on a mode of operation.

摘要翻译： 一种半导体存储器件，包括用于调节外部电源电压并产生第一和第二内部电源电压的内部电压发生器电路。 第一内部电源电压经由第一电源线提供给存储单元阵列，并且第二内部电源电压经由第二电源线提供给外围电路。 控制电路控制内部电压发生器电路，使得第一和第二内部电源电压的电平根据操作模式而变化。

公开(公告)号：US5805012A

公开(公告)日：1998-09-08

申请号：US653438

申请日：1996-05-24

申请人： Byung-Gil Jeon ,  Chul-Sung Park

发明人： Byung-Gil Jeon ,  Chul-Sung Park

IPC分类号： G11C11/417 ,  G11C5/14 ,  H01L21/8234 ,  H01L27/06 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/08 ,  H03K17/14

CPC分类号： H03K19/00384

摘要： The speed gap between rise and fall times of a buffer biased by a power supply having a power supply voltage, the speed gap varying in a first manner with respect to the power supply voltage and in a second manner inverse to the first manner with respect to a bias current supplied to the buffer, is controlled by generating the bias current such that the bias current varies inversely with respect to the power supply voltage, thereby compensating for fluctuations in the power supply voltage and maintaining the speed gap within a predetermined range when the power supply voltage is greater than a power supply voltage threshold level. The buffer may include a bias transistor controlling the bias current, with the bias current controlled by regulating the differential voltage applied to a control electrode of the bias transistor with an inverse voltage regulator including a control voltage generator for generating a control voltage varying directly with respect to the power supply voltage when the power supply voltage is less than the power supply voltage threshold level and remaining at a control voltage set point level when the power supply voltage is greater than the power supply voltage threshold level, a current feedback regulator for varying the feedback current directly with respect to the power supply voltage, and an output voltage generator for generating the differential voltage from the feedback current and the control voltage such that when the control voltage is at the control voltage set point level, the differential voltage varies inversely with respect to the feedback current.

摘要翻译： 由具有电源电压的电源偏置的缓冲器的上升和下降时间之间的速度差，相对于电源电压以第一种方式变化的速度间隙，以与第一种方式相反的第二种方式相对于 通过产生偏置电流来控制提供给缓冲器的偏置电流，使得偏置电流相对于电源电压反向变化，从而补偿电源电压的波动并且将速度间隙保持在预定范围内，当 电源电压大于电源电压阈值电平。 缓冲器可以包括控制偏置电流的偏置晶体管，偏置电流通过利用包括用于产生直接变化的控制电压的控制电压发生器的反向电压调节器调节施加到偏置晶体管的控制电极的差分电压来控制， 当电源电压小于电源电压阈值电平并且当电源电压大于电源电压阈值电平时保持在控制电压设定点电平时，提供电源电压;电流反馈调节器，用于改变电源电压 反馈电流直接相对于电源电压，以及输出电压发生器，用于从反馈电流和控制电压产生差分电压，使得当控制电压处于控制电压设定点电平时，差分电压与 尊重反馈电流。

公开(公告)号：US09076548B1

公开(公告)日：2015-07-07

申请号：US14056995

申请日：2013-10-18

申请人： Duk-Ha Park ,  Chul-Sung Park ,  Jung-Bae Lee

发明人： Duk-Ha Park ,  Chul-Sung Park ,  Jung-Bae Lee

IPC分类号： G11C7/00 ,  G11C11/402

CPC分类号： G11C5/02 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C13/0033 ,  G11C16/3418

摘要： A method of refreshing a semiconductor memory device includes performing a first refresh operation for memory cells included in a memory cell array, and determining whether a command other than a refresh command is applied to the semiconductor memory device in a refresh cycle of the first refresh operation. The method further includes continuing to perform the first refresh operation when a command other the refresh command is applied to the semiconductor memory device in one refresh cycle of the first refresh operation, and performing a second refresh operation when a command other than the refresh command is not applied to the semiconductor memory device in one refresh cycle of the first refresh operation. A refresh time of the second refresh operation is greater than a refresh time of the first refresh operation.

摘要翻译： 一种刷新半导体存储器件的方法包括对包含在存储单元阵列中的存储单元执行第一刷新操作，并且在第一刷新操作的刷新周期中确定除刷新命令之外的命令是否被应用于半导体存储器件 。 该方法还包括当在第一刷新操作的一个刷新周期中将另外刷新命令的命令施加到半导体存储器件的命令时继续执行第一刷新操作，并且当除了刷新命令之外的命令是执行第二刷新操作时 在第一刷新操作的一个刷新周期中不施加到半导体存储器件。 第二刷新操作的刷新时间大于第一刷新操作的刷新时间。

公开(公告)号：US07902871B2

公开(公告)日：2011-03-08

申请号：US12759252

申请日：2010-04-13

申请人： Yong-Hwan Noh ,  Chul-Sung Park

发明人： Yong-Hwan Noh ,  Chul-Sung Park

IPC分类号： H03K19/0175

CPC分类号： H03K19/018528

摘要： Provided are a level shifter and a semiconductor device having an OFF-chip driver (OCD) using the same. The level shifter includes a plurality of series connected logic gates receiving a first-state input signal having a first power supply voltage level and generating a level-shifted first-state output signal having a second power supply voltage level. The logic gates receive as power supply voltages at least one intermediate power supply voltage having at least one voltage level intermediate between the first power supply voltage level and the second power supply voltage level, and an intermediate power supply voltage applied to the present logic gate is equal to or higher than an intermediate power supply voltage applied to the previous logic gate.

摘要翻译： 提供了一种电平转换器和具有使用其的片外驱动器（OCD）的半导体器件。 电平移位器包括多个串联连接的逻辑门，其接收具有第一电源电压电平的第一状态输入信号，并产生具有第二电源电压电平的电平移位的第一状态输出信号。 逻辑门作为电源电压接收至少一个中间电源电压，其具有在第一电源电压电平和第二电源电压电平之间的中间的至少一个电压电平，并且施加到本逻辑门的中间电源电压为 等于或高于施加到先前逻辑门的中间电源电压。

公开(公告)号：US20050276126A1

公开(公告)日：2005-12-15

申请号：US11153755

申请日：2005-06-14

申请人： Myung-Han Choi ,  Young-Dae Lee ,  Chul-Sung Park

发明人： Myung-Han Choi ,  Young-Dae Lee ,  Chul-Sung Park

IPC分类号： H03K19/0175 ,  G11C5/00 ,  H03K19/00

CPC分类号： H03K19/0005

摘要： A programmable impedance control circuit for use in a semiconductor device having an impedance range shifting function prevents or substantially reduces an impedance detection failure based on an environment change. An impedance detector includes a first array driver, a second array driver, and an impedance matching transistor array and a range shifting transistor array independently controlled by the first and second array drivers. A comparator each compares first and second output voltage levels of the impedance detector with an array reference voltage, and outputs an up/down signal as the comparison result. A counter performs an up/down counting in response to the up/down signal, and outputs control code data. A range shifting circuit monitors a counting output of the counter and so generates range shifting data. Whereby, even if there is an environment change on a manufacturing process, power source voltage or operating temperature, etc., an impedance matching and correction operation can be performed without a waste of impedance matching transistor array and control code.

摘要翻译： 用于具有阻抗范围移位功能的半导体器件中的可编程阻抗控制电路防止或基本上减少了基于环境变化的阻抗检测失败。 阻抗检测器包括第一阵列驱动器，第二阵列驱动器和阻抗匹配晶体管阵列以及由第一和第二阵列驱动器独立控制的量程移位晶体管阵列。 比较器每个将阻抗检测器的第一和第二输出电压电平与阵列参考电压进行比较，并输出上/下信号作为比较结果。 计数器响应于上/下信号执行向上/向下计数，并输出控制代码数据。 范围移动电路监视计数器的计数输出，因此产生范围移位数据。 因此，即使在制造过程中存在环境变化，电源电压或工作温度等，也可以进行阻抗匹配和校正操作，而不会浪费阻抗匹配晶体管阵列和控制代码。

公开(公告)号：US06822330B2

公开(公告)日：2004-11-23

申请号：US10346019

申请日：2003-01-16

申请人： Chul-Sung Park ,  Yong-Hwan Noh ,  Byong-Kwon Lee ,  Hyang-Ja Yang

发明人： Chul-Sung Park ,  Yong-Hwan Noh ,  Byong-Kwon Lee ,  Hyang-Ja Yang

IPC分类号： H01L2348

CPC分类号： H01L22/34 ,  G01R31/2884

摘要： Disclosed is a semiconductor integrated circuit device which includes a test element group circuit connected between a first and a second pad. The test element group circuit includes a plurality of semiconductor devices connected in series between the first and second pads. At least two adjacent ones of the semiconductor devices are connected to each other via a signal path that is formed by a multi-layer interconnection structure.

摘要翻译： 公开了一种半导体集成电路器件，其包括连接在第一和第二焊盘之间的测试元件组电路。 测试元件组电路包括串联连接在第一和第二焊盘之间的多个半导体器件。 至少两个相邻的半导体器件通过由多层互连结构形成的信号路径相互连接。

公开(公告)号：US08638626B2

公开(公告)日：2014-01-28

申请号：US13237353

申请日：2011-09-20

申请人： Hui-Kap Yang ,  Woo-Seop Jeong ,  Chul-Sung Park

发明人： Hui-Kap Yang ,  Woo-Seop Jeong ,  Chul-Sung Park

IPC分类号： G11C7/00

CPC分类号： G11C29/20 ,  G11C2029/1802

摘要： A row address control circuit of a semiconductor memory device including dynamic memory cells includes a test mode setting unit, an address counter and a row address generating unit. The test mode setting unit is configured to provide a test mode signal that indicates whether a test operation is performed or not, in response to a test command; the address counter is configured to generate a first address that increases gradually; and the row address generating unit is configured to selectively choose one of the first address and a second address as a refresh address based on the test mode signal, the second address being externally provided.

摘要翻译： 包括动态存储单元的半导体存储器件的行地址控制电路包括测试模式设置单元，地址计数器和行地址生成单元。 测试模式设置单元被配置为响应于测试命令提供指示是否执行测试操作的测试模式信号; 地址计数器被配置为生成逐渐增加的第一地址; 并且行地址生成单元被配置为基于测试模式信号选择性地选择第一地址和第二地址中的一个作为刷新地址，第二地址被外部提供。