Abstract:
A semiconductor device 100 of the present invention includes a front end and back ends A and B, each including a plurality of layers. Further, in the plurality of layers of the back end B, (i) circuits 22, 23, and 24 having a security function are provided in at least one layer having a wiring pitch of 100 nm or more, (ii) a circuit having a security function is provided in at least one wiring layer in M5 or higher level (M5, M6, M7, . . . ), (iii) a circuit having a security function is provided in at least one layer, for which immersion ArF exposure does not need to be used, or (iv) a circuit having a security function is provided in at least one layer that is exposed by using an exposure wavelength of 200 nm or more.
Abstract:
A tunnel path of the tunnel FET at a source-gate overlap portion is divided into a vertical path vertical to the source-gate overlap portion and a horizontal path extending to a drain in a horizontal direction along a channel interface. A tunnel distance computation section obtains a tunnel distance for each position of a nonlocal electric field band-to-band tunnel, using first and second bends of the mid-gap potential, which are previously stored approximate functions of the mid-gap potential on the vertical and horizontal paths, respectively. A carrier generation rate computation section computes a carrier generation rate due to band-to-band tunneling, based on the tunnel distance at each position of the nonlocal electric field band-to-band tunnel and a band gap.
Abstract:
The present invention provides a field-effect transistor having an accumulation-layer-operation type field-effect transistor that includes a semiconductor layer in which a source region, a channel region, and a drain region that have either an N-type or P-type conductivity in common are formed, and a gate electrode disposed adjacent to the channel region via a gate insulating film, wherein the gate insulating film is made of a dielectric having a change gradient of a relative dielectric constant in which the relative dielectric constant changes to decrease according to the magnitude of a gate voltage applied to the gate electrode.