公开(公告)号：US20200243687A1

公开(公告)日：2020-07-30

申请号：US16650928

申请日：2018-09-11

Applicant: National Institute of Advanced Industrial Science and Technology

Inventor： Hiroyuki Ota ,  Shinji Migita

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L27/1159 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: Power consumption of a semiconductor device is reduced by sharpening the rise of a drain current when a gate voltage of a field effect transistor is less than a threshold voltage. As means therefor, in a fully-depleted MOSFET in which a thickness of a semiconductor layer serving as a channel region is 20 nm or less, a gate plug connected to a gate electrode is constituted of a first plug, a ferroelectric film, and a second plug sequentially stacked on the gate electrode. Here, an area where a contact surface between the first plug and the ferroelectric film and a contact surface between the ferroelectric film and the second plug overlap in a plan view is smaller than an area where the gate electrode and a semiconductor layer serving as an active region overlap.

公开(公告)号：US20190019766A1

公开(公告)日：2019-01-17

申请号：US15750614

申请日：2016-08-03

Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY

Inventor： Yohei Hori ,  Yongxun Liu ,  Shinichi Ouchi ,  Tetsuji Yasuda ,  Meishoku Masahara ,  Toshifumi Irisawa ,  Kazuhiko Endo ,  Hiroyuki Ota ,  Tatsuro Maeda ,  Hanpei Koike ,  Yasuhiro Ogasahara ,  Toshihiro Katashita ,  Koichi Fukuda

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/522

Abstract: A semiconductor device 100 of the present invention includes a front end and back ends A and B, each including a plurality of layers. Further, in the plurality of layers of the back end B, (i) circuits 22, 23, and 24 having a security function are provided in at least one layer having a wiring pitch of 100 nm or more, (ii) a circuit having a security function is provided in at least one wiring layer in M5 or higher level (M5, M6, M7, . . . ), (iii) a circuit having a security function is provided in at least one layer, for which immersion ArF exposure does not need to be used, or (iv) a circuit having a security function is provided in at least one layer that is exposed by using an exposure wavelength of 200 nm or more.

公开(公告)号：US11114565B2

公开(公告)日：2021-09-07

申请号：US16650928

申请日：2018-09-11

Applicant: National Institute of Advanced Industrial Science and Technology

Inventor： Hiroyuki Ota ,  Shinji Migita

IPC: H01L29/78 ,  H01L29/40 ,  H01L21/28 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L27/1159 ,  H01L29/06 ,  H01L29/51 ,  H01L29/66

Abstract: Power consumption of a semiconductor device is reduced by sharpening the rise of a drain current when a gate voltage of a field effect transistor is less than a threshold voltage. As means therefor, in a fully-depleted MOSFET in which a thickness of a semiconductor layer serving as a channel region is 20 nm or less, a gate plug connected to a gate electrode is constituted of a first plug, a ferroelectric film, and a second plug sequentially stacked on the gate electrode. Here, an area where a contact surface between the first plug and the ferroelectric film and a contact surface between the ferroelectric film and the second plug overlap in a plan view is smaller than an area where the gate electrode and a semiconductor layer serving as an active region overlap.

公开(公告)号：US09698235B2

公开(公告)日：2017-07-04

申请号：US15031110

申请日：2014-08-12

Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY

Inventor： Shinji Migita ,  Hiroyuki Ota ,  Koichi Fukuda

IPC: H01L21/02 ,  H01L29/51 ,  H01L29/78 ,  H01L29/49 ,  H01L29/786 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20

CPC classification number: H01L29/513 ,  H01L21/02197 ,  H01L21/02266 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78654 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

Abstract: The present invention provides a field-effect transistor having an accumulation-layer-operation type field-effect transistor that includes a semiconductor layer in which a source region, a channel region, and a drain region that have either an N-type or P-type conductivity in common are formed, and a gate electrode disposed adjacent to the channel region via a gate insulating film, wherein the gate insulating film is made of a dielectric having a change gradient of a relative dielectric constant in which the relative dielectric constant changes to decrease according to the magnitude of a gate voltage applied to the gate electrode.