公开(公告)号：US20240143408A1

公开(公告)日：2024-05-02

申请号：US17978885

申请日：2022-11-01

Applicant: NVIDIA Corporation

Inventor： Andrew Currid ,  Anshul Fadnavis ,  Chenghuan Jia ,  Ankit Agrawal

IPC: G06F9/50

CPC classification number: G06F9/505 ,  G06F9/5044 ,  G06F2209/5019 ,  G06F2209/505

Abstract: Apparatuses, systems, and techniques to determine metrics for paths connecting hardware components, select a plurality of groups of the hardware components based at least in part on the metrics, and perform at least a portion of a workload using a selected group of the plurality of groups.

公开(公告)号：US09798487B2

公开(公告)日：2017-10-24

申请号：US15243909

申请日：2016-08-22

Applicant: NVIDIA Corporation

Inventor： Jerome F. Duluk, Jr. ,  Cameron Buschardt ,  James Leroy Deming ,  Lucien Dunning ,  Brian Fahs ,  Mark Hairgrove ,  Chenghuan Jia ,  John Mashey ,  James M. Van Dyke

IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06 ,  G06F12/08 ,  G06F12/1009 ,  G06F12/122

CPC classification number: G06F3/0647 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0683 ,  G06F12/08 ,  G06F12/1009 ,  G06F12/122 ,  G06F2212/652

Abstract: One embodiment of the present invention sets forth a computer-implemented method for migrating a memory page from a first memory to a second memory. The method includes determining a first page size supported by the first memory. The method also includes determining a second page size supported by the second memory. The method further includes determining a use history of the memory page based on an entry in a page state directory associated with the memory page. The method also includes migrating the memory page between the first memory and the second memory based on the first page size, the second page size, and the use history.

公开(公告)号：US10216413B2

公开(公告)日：2019-02-26

申请号：US15583920

申请日：2017-05-01

Applicant: NVIDIA Corporation

Inventor： Jerome F. Duluk, Jr. ,  John Mashey ,  Mark Hairgrove ,  Chenghuan Jia ,  Cameron Buschardt ,  Lucien Dunning ,  Brian Fahs

IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06 ,  G06F12/1009 ,  G06F12/0804 ,  G06F13/40 ,  G06F13/42

Abstract: Techniques are provided by which memory pages may be migrated among PPU memories in a multi-PPU system. According to the techniques, a UVM driver determines that a particular memory page should change ownership state and/or be migrated between one PPU memory and another PPU memory. In response to this determination, the UVM driver initiates a peer transition sequence to cause the ownership state and/or location of the memory page to change. Various peer transition sequences involve modifying mappings for one or more PPU, and copying a memory page from one PPU memory to another PPU memory. Several steps in peer transition sequences may be performed in parallel for increased processing speed.

公开(公告)号：US10031856B2

公开(公告)日：2018-07-24

申请号：US14055367

申请日：2013-10-16

Applicant: NVIDIA Corporation

Inventor： Jerome F. Duluk, Jr. ,  Chenghuan Jia ,  John Mashey ,  Cameron Buschardt ,  Sherry Cheung ,  James Leroy Deming ,  Samuel H. Duncan ,  Lucien Dunning ,  Robert George ,  Arvind Gopalakrishnan ,  Mark Hairgrove

IPC: G06F3/00 ,  G06F12/1009 ,  G06F12/10

CPC classification number: G06F12/1009 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1072 ,  G06F12/109 ,  G06F12/12 ,  G06F2212/1016

Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

公开(公告)号：US09424201B2

公开(公告)日：2016-08-23

申请号：US14134142

申请日：2013-12-19

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. Duluk, Jr. ,  Cameron Buschardt ,  James Leroy Deming ,  Lucien Dunning ,  Brian Fahs ,  Mark Hairgrove ,  Chenghuan Jia ,  John Mashey ,  James M. Van Dyke

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/10 ,  G06F12/08 ,  G06F12/12

CPC classification number: G06F3/0647 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0683 ,  G06F12/08 ,  G06F12/1009 ,  G06F12/122 ,  G06F2212/652

Abstract: One embodiment of the present invention sets forth a computer-implemented method for migrating a memory page from a first memory to a second memory. The method includes determining a first page size supported by the first memory. The method also includes determining a second page size supported by the second memory. The method further includes determining a use history of the memory page based on an entry in a page state directory associated with the memory page. The method also includes migrating the memory page between the first memory and the second memory based on the first page size, the second page size, and the use history.

Abstract translation: 本发明的一个实施例提出了一种用于将存储器页从第一存储器迁移到第二存储器的计算机实现的方法。 该方法包括确定由第一存储器支持的第一页大小。 该方法还包括确定由第二存储器支持的第二页大小。 该方法还包括基于与存储器页相关联的页面状态目录中的条目来确定存储器页面的使用历史。 该方法还包括基于第一页面大小，第二页面大小和使用历史来在第一存储器和第二存储器之间迁移存储器页面。

公开(公告)号：US11966765B2

公开(公告)日：2024-04-23

申请号：US17015377

申请日：2020-09-09

Applicant: NVIDIA Corporation

Inventor： Santosh Kumar Ravindranath Shukla ,  Andrew Currid ,  Chenghuan Jia ,  Arpit R. Jain ,  Shounak Santosh Deshpande

IPC: G06F9/455 ,  G06N3/04 ,  G06N3/08 ,  A63F13/30

CPC classification number: G06F9/45558 ,  G06N3/04 ,  G06N3/08 ,  A63F13/30 ,  G06F2009/45583

Abstract: Systems and methods are disclosed for throttling memory bandwidth accessed by virtual machines (VMs). A technique for dynamically throttling the virtual computer processing units (vCPUs) assigned to a VM (tenant) controls the memory access rate of the VM. When the memory is shared by multiple VMs in a cloud-computing environment, one VM increasing its memory access rate may cause another VM to suffer memory access starvation. This behavior violates the principle of VM isolation in cloud computing. In contrast to conventional systems, a software solution for dynamically throttling the vCPUs may be implemented within a hypervisor and is therefore portable across CPU families and doesn't require specialized server-class CPU capabilities or limit the system configuration.

公开(公告)号：US11741015B2

公开(公告)日：2023-08-29

申请号：US17820870

申请日：2022-08-18

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. Duluk, Jr. ,  Cameron Buschardt ,  Sherry Cheung ,  James Leroy Deming ,  Samuel H. Duncan ,  Lucien Dunning ,  Robert George ,  Arvind Gopalakrishnan ,  Mark Hairgrove ,  Chenghuan Jia ,  John Mashey

IPC: G06F11/07 ,  G06F12/08 ,  G06F12/1072 ,  G06F12/109 ,  G06F12/12 ,  G06F12/10 ,  G06F12/1009

CPC classification number: G06F12/1009 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/08 ,  G06F12/109 ,  G06F12/1072 ,  G06F12/12 ,  G06F12/10 ,  G06F2212/1016

Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

公开(公告)号：US09495723B2

公开(公告)日：2016-11-15

申请号：US14026410

申请日：2013-09-13

Applicant: NVIDIA Corporation

Inventor： Andrew Currid ,  Franck Diard ,  Chenghuan Jia ,  Parag Kulkarni

IPC: G06F3/00 ,  G06F13/28 ,  G06F13/00 ,  G06T1/20 ,  G09G5/36 ,  G06F9/46 ,  G06F3/14 ,  G06F9/455 ,  G06F9/50 ,  G09G3/00

CPC classification number: G06T1/20 ,  G06F3/1438 ,  G06F9/455 ,  G06F9/46 ,  G06F9/5077 ,  G09G3/003 ,  G09G5/363 ,  G09G2360/06 ,  G09G2370/022

Abstract: A device for processing graphics data includes a plurality of graphics processing units. Each graphics processing unit may correspond to a virtualized operating system. Each graphics processing unit may include a configuration register indicating a 3D class code and a command register indicating that I/O cycle decoding is disabled. The device may be configured to transmit a configuration register value to a virtualized operating system indicating a VGA-compatible class code. The device may be configured to transmit a command register value to the virtualized operating system that indicates that I/O cycle decoding is enabled. In this manner, legacy bus architecture of the device may not limit the number of graphics processing units deployed in the device.

Abstract translation: 用于处理图形数据的设备包括多个图形处理单元。 每个图形处理单元可以对应于虚拟化的操作系统。 每个图形处理单元可以包括指示3D类代码的配置寄存器和指示I / O周期解码被禁用的命令寄存器。 该设备可以被配置为将配置寄存器值发送到指示VGA兼容类代码的虚拟操作系统。 该设备可以被配置为向指示执行I / O周期解码的虚拟化操作系统发送命令寄存器值。 以这种方式，设备的传统总线架构可能不限制部署在设备中的图形处理单元的数量。

公开(公告)号：US20220075638A1

公开(公告)日：2022-03-10

申请号：US17015377

申请日：2020-09-09

Applicant: NVIDIA Corporation

Inventor： Santosh Kumar Ravindranath Shukla ,  Andrew Currid ,  Chenghuan Jia ,  Arpit R. Jain ,  Shounak Santosh Deshpande

IPC: G06F9/455 ,  G06N3/04 ,  G06N3/08

Abstract: Systems and methods are disclosed for throttling memory bandwidth accessed by virtual machines (VMs). A technique for dynamically throttling the virtual computer processing units (vCPUs) assigned to a VM (tenant) controls the memory access rate of the VM. When the memory is shared by multiple VMs in a cloud-computing environment, one VM increasing its memory access rate may cause another VM to suffer memory access starvation. This behavior violates the principle of VM isolation in cloud computing. In contrast to conventional systems, a software solution for dynamically throttling the vCPUs may be implemented within a hypervisor and is therefore portable across CPU families and doesn't require specialized server-class CPU capabilities or limit the system configuration.

公开(公告)号：US10445243B2

公开(公告)日：2019-10-15

申请号：US14055356

申请日：2013-10-16

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. Duluk, Jr. ,  Cameron Buschardt ,  Sherry Cheung ,  James Leroy Deming ,  Samuel H. Duncan ,  Lucien Dunning ,  Robert George ,  Arvind Gopalakrishnan ,  Mark Hairgrove ,  Chenghuan Jia ,  John Mashey

IPC: G06F13/12 ,  G06F13/38 ,  G06F12/1009 ,  G06F12/109 ,  G06F12/1072 ,  G06F11/07 ,  G06F12/12 ,  G06F12/08 ,  G06F12/10

Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.