公开(公告)号：US20150235695A1

公开(公告)日：2015-08-20

申请号：US14282809

申请日：2014-05-20

Applicant: Nvidia Corporation

Inventor： Gang Chen ,  Jing Guo ,  Jun Yang

IPC: G11C11/419 ,  G11C5/14

CPC classification number: G11C11/419 ,  G11C5/147

Abstract: A write-assist memory includes a memory supply voltage and a column of SRAM cells that is controlled by a pair of bit lines, during a write operation. Additionally, the write-assist memory includes a write-assist unit that is coupled to the memory supply voltage and the column of SRAM cells and has a separable conductive line located between the pair of bit lines that provides a collapsible SRAM supply voltage to the column of SRAM cells based on a capacitive coupling of a control signal in the pair of bit lines, during the write operation. A method of operating a write-assist memory is also provided.

Abstract translation: 在写操作期间，写辅助存储器包括由一对位线控制的存储器电源电压和一列SRAM单元。 另外，写辅助存储器包括写辅助单元，其耦合到存储器电源电压和SRAM单元列，并且具有位于该对位线之间的可分离导线，该可分离导线向列提供可折叠的SRAM供电电压 在写操作期间基于位线对中的控制信号的电容耦合的SRAM单元。 还提供了一种操作写辅助存储器的方法。

公开(公告)号：US09640249B2

公开(公告)日：2017-05-02

申请号：US14282809

申请日：2014-05-20

Applicant: Nvidia Corporation

Inventor： Gang Chen ,  Jing Guo ,  Jun Yang

IPC: G11C11/00 ,  G11C11/419 ,  G11C5/14

CPC classification number: G11C11/419 ,  G11C5/147

Abstract: A write-assist memory includes a memory supply voltage and a column of SRAM cells that is controlled by a pair of bit lines, during a write operation. Additionally, the write-assist memory includes a write-assist unit that is coupled to the memory supply voltage and the column of SRAM cells and has a separable conductive line located between the pair of bit lines that provides a collapsible SRAM supply voltage to the column of SRAM cells based on a capacitive coupling of a control signal in the pair of bit lines, during the write operation. A method of operating a write-assist memory is also provided.

公开(公告)号：US09484115B1

公开(公告)日：2016-11-01

申请号：US14711712

申请日：2015-05-13

Applicant: NVIDIA CORPORATION

Inventor： Stephen Felix ,  Hwong-Kwo Lin ,  Spencer Gold ,  Jing Guo ,  Andreas Gotterba ,  Jason Golbus ,  Karthik Natarajan ,  Jun Yang ,  Zhenye Jiang ,  Ge Yang ,  Lei Wang ,  Yong Li ,  Hua Chen ,  Haiyan Gong ,  Beibei Ren ,  Eric Voelkel

IPC: G11C29/08 ,  G11C11/16 ,  G11C7/00 ,  G11C5/14

CPC classification number: G11C11/1697 ,  G11C5/143 ,  G11C7/00 ,  G11C11/417 ,  G11C29/08 ,  G11C2207/2227

Abstract: A subsystem configured to select the power supply to a static random access memory cell compares the level of a dedicated memory supply voltage to the primary system supply voltage. The subsystem then switches the primary system supply to the SRAM cell when the system voltage is higher than the memory supply voltage with some margin. When the system voltage is lower than the memory supply voltage, with margin, the subsystem switches the memory supply to the SRAM cell. When the system voltage is comparable to the memory supply, the subsystem switches the system voltage to the SRAM cell if performance is a prioritized consideration, but switches the memory supply to the SRAM cell if power reduction is a prioritized consideration. In this manner, the system achieves optimum performance without incurring steady state power losses and avoids timing issues in accessing memory.

Abstract translation: 被配置为选择对静态随机存取存储器单元的电源的子系统将专用存储器电源电压的电平与主系统电源电压进行比较。 当系统电压高于具有一定余量的存储器电源电压时，子系统将主系统电源切换到SRAM单元。 当系统电压低于存储器电源电压时，子系统将存储器电源切换到SRAM单元。 当系统电压与存储器电源相当时，如果性能是优先考虑的话，子系统将系统电压切换到SRAM单元，但如果降低功耗是优先考虑的话，将存储器电源切换到SRAM单元。 以这种方式，系统实现最佳性能而不会导致稳态功率损耗，并避免访问存储器时的定时问题。

公开(公告)号：US20140347916A1

公开(公告)日：2014-11-27

申请号：US13901614

申请日：2013-05-24

Applicant: NVIDIA Corporation

Inventor： Jun Yang ,  Hwong-Kwo Lin ,  Ju Shen ,  Yong Li ,  Hua Chen

IPC: G11C11/412 ,  G11C11/419

CPC classification number: G11C11/412 ,  G11C11/419

Abstract: Disclosed are devices, systems and/or methods relating to an eight transistor (8T) static random access memory (SRAM) cell, according to one or more embodiments. In one embodiment, an SRAM storage cell is disclosed comprising a word line, a write column select line, a cross-coupled data latch, and a first NMOS switch device serially coupled to a second NMOS switch device. In this embodiment, the gate node of the first NMOS switch device is coupled to the word line, a source node of the first NMOS switch device is coupled to the cross-coupled data latch, a gate node of the second NMOS switch device is coupled to the write column select line, and a source node of the second NMOS switch device is coupled to the cross-coupled data latch.

Abstract translation: 公开了根据一个或多个实施例的与八晶体管（8T）静态随机存取存储器（SRAM）单元相关的器件，系统和/或方法。 在一个实施例中，公开了一种SRAM存储单元，其包括字线，写列选择线，交叉耦合数据锁存器和串联耦合到第二NMOS开关器件的第一NMOS开关器件。 在该实施例中，第一NMOS开关器件的栅极节点耦合到字线，第一NMOS开关器件的源节点耦合到交叉耦合数据锁存器，第二NMOS开关器件的栅极节点被耦合 到写列选择线，并且第二NMOS开关器件的源节点耦合到交叉耦合数据锁存器。

公开(公告)号：US09183922B2

公开(公告)日：2015-11-10

申请号：US13901614

申请日：2013-05-24

Applicant: NVIDIA Corporation

Inventor： Jun Yang ,  Hwong-Kwo Lin ,  Ju Shen ,  Yong Li ,  Hua Chen

IPC: G11C11/00 ,  G11C11/412 ,  G11C11/419

CPC classification number: G11C11/412 ,  G11C11/419

Abstract: Disclosed are devices, systems and/or methods relating to an eight transistor (8T) static random access memory (SRAM) cell, according to one or more embodiments. In one embodiment, an SRAM storage cell is disclosed comprising a word line, a write column select line, a cross-coupled data latch, and a first NMOS switch device serially coupled to a second NMOS switch device. In this embodiment, the gate node of the first NMOS switch device is coupled to the word line, a source node of the first NMOS switch device is coupled to the cross-coupled data latch, a gate node of the second NMOS switch device is coupled to the write column select line, and a source node of the second NMOS switch device is coupled to the cross-coupled data latch.

Abstract translation: 公开了根据一个或多个实施例的与八晶体管（8T）静态随机存取存储器（SRAM）单元相关的器件，系统和/或方法。 在一个实施例中，公开了一种SRAM存储单元，其包括字线，写列选择线，交叉耦合数据锁存器和串联耦合到第二NMOS开关器件的第一NMOS开关器件。 在该实施例中，第一NMOS开关器件的栅极节点耦合到字线，第一NMOS开关器件的源节点耦合到交叉耦合数据锁存器，第二NMOS开关器件的栅极节点被耦合 到写列选择线，并且第二NMOS开关器件的源节点耦合到交叉耦合数据锁存器。