公开(公告)号：US20160026195A1

公开(公告)日：2016-01-28

申请号：US14876332

申请日：2015-10-06

Applicant: Nvidia Corporation

Inventor： Brian L. Smith ,  Stephen Felix ,  Jesse Max Guss ,  Tezaswi Raja

IPC: G05F1/46

CPC classification number: G05F1/465 ,  G05F1/462

Abstract: A voltage margin controller, an IC included the same and a method of controlling voltage margin for a voltage domain of an IC are disclosed herein. In one embodiment, the voltage margin controller includes: (1) monitoring branches including circuit function indicators configured to indicate whether circuitry in the voltage domain could operate at corresponding candidate reduced voltage levels and (2) a voltage margin adjuster coupled to the monitoring branches and configured to develop a voltage margin adjustment for a voltage regulator of the voltage domain based upon an operating number of the circuit function indicators.

公开(公告)号：US20150212149A1

公开(公告)日：2015-07-30

申请号：US14163066

申请日：2014-01-24

Applicant: Nvidia Corporation

Inventor： Brian Smith ,  Stephen Felix ,  Tezaswi Raja ,  Roman Surgutchik

IPC: G01R31/28 ,  G01R1/30

CPC classification number: G01R31/2858 ,  G01R1/30 ,  G01R31/2837 ,  G01R31/2851 ,  G01R31/31727 ,  H03K3/0315

Abstract: A degradation detector for an integrated circuit (IC), a method of detecting aging in an IC and an IC incorporating the degradation detector or the method. In one embodiment, the degradation detector includes: (1) an offline ring oscillator (RO) coupled to a power gate and a clock gate, (2) a frozen RO coupled to a clock gate, (3) an online RO and (4) an analyzer coupled to the offline RO, the frozen RO and the online RO and operable to place the degradation detector in a normal state in which the offline RO is disconnected from both the drive voltage source and the clock source, the frozen RO is connected to the drive voltage source but disconnected from the clock source and the online RO is connected to both the drive voltage source and the clock source.

Abstract translation: 用于集成电路（IC）的劣化检测器，检测IC中的老化的方法和结合了劣化检测器的IC或方法。 在一个实施例中，劣化检测器包括：（1）耦合到功率门和时钟门的离线环形振荡器（RO），（2）耦合到时钟门的冷冻RO，（3）在线RO和（4） ）分析器，其耦合到离线RO，冷冻RO和在线RO，并且可操作以将劣化检测器置于正常状态，其中脱机RO与驱动电压源和时钟源两者断开，冷冻RO连接 到驱动电压源但与时钟源断开，并且在线RO连接到驱动电压源和时钟源。

公开(公告)号：US09007113B1

公开(公告)日：2015-04-14

申请号：US14149477

申请日：2014-01-07

Applicant: NVIDIA Corporation

Inventor： Stephen Felix ,  Stéphane Badel

IPC: H03K3/037

CPC classification number: H03K3/037 ,  H03K3/356121

Abstract: According to one aspect of the present disclosure, there is provided a flip flop circuit, comprising a first input circuit configured to receive a clock input signal and input data and comprising a first node. The flip-clop circuit further comprises a second input circuit configured to receive the input data and an inverse of the clock signal and comprising a second node. The first and second input circuits are configured such that the first node and the second node are pre-charged to respective complementary states when the clock signal is at a first level and, dependent on a value of the input data, one of said first and second nodes changes state to a state complementary to its pre-charged state when the clock signal transitions from the first level to a second level.

Abstract translation: 根据本公开的一个方面，提供了一种触发器电路，包括被配置为接收时钟输入信号和输入数据并包括第一节点的第一输入电路。 触发器电路还包括被配置为接收输入数据和时钟信号的反相并包括第二节点的第二输入电路。 第一和第二输入电路配置成使得当时钟信号处于第一电平时，第一节点和第二节点被预充电到相应的互补状态，并且根据输入数据的值，所述第一和第二节点之一 当时钟信号从第一电平转变到第二电平时，第二节点将状态改变为与其预充电状态互补的状态。

公开(公告)号：US09494641B2

公开(公告)日：2016-11-15

申请号：US14163066

申请日：2014-01-24

Applicant: Nvidia Corporation

Inventor： Brian Smith ,  Stephen Felix ,  Tezaswi Raja ,  Roman Surgutchik

IPC: G01R31/28 ,  G01R31/317 ,  H03K3/03 ,  G01R1/30

CPC classification number: G01R31/2858 ,  G01R1/30 ,  G01R31/2837 ,  G01R31/2851 ,  G01R31/31727 ,  H03K3/0315

Abstract: A degradation detector for an integrated circuit (IC), a method of detecting aging in an IC and an IC incorporating the degradation detector or the method. In one embodiment, the degradation detector includes: (1) an offline ring oscillator (RO) coupled to a power gate and a clock gate, (2) a frozen RO coupled to a clock gate, (3) an online RO and (4) an analyzer coupled to the offline RO, the frozen RO and the online RO and operable to place the degradation detector in a normal state in which the offline RO is disconnected from both the drive voltage source and the clock source, the frozen RO is connected to the drive voltage source but disconnected from the clock source and the online RO is connected to both the drive voltage source and the clock source.

Abstract translation: 用于集成电路（IC）的劣化检测器，检测IC中的老化的方法和结合了劣化检测器的IC或方法。 在一个实施例中，劣化检测器包括：（1）耦合到功率门和时钟门的离线环形振荡器（RO），（2）耦合到时钟门的冷冻RO，（3）在线RO和（4） ）分析器，其耦合到离线RO，冷冻RO和在线RO，并且可操作以将劣化检测器置于正常状态，其中脱机RO与驱动电压源和时钟源两者断开，冷冻RO连接 到驱动电压源但与时钟源断开，并且在线RO连接到驱动电压源和时钟源。

公开(公告)号：US09484115B1

公开(公告)日：2016-11-01

申请号：US14711712

申请日：2015-05-13

Applicant: NVIDIA CORPORATION

Inventor： Stephen Felix ,  Hwong-Kwo Lin ,  Spencer Gold ,  Jing Guo ,  Andreas Gotterba ,  Jason Golbus ,  Karthik Natarajan ,  Jun Yang ,  Zhenye Jiang ,  Ge Yang ,  Lei Wang ,  Yong Li ,  Hua Chen ,  Haiyan Gong ,  Beibei Ren ,  Eric Voelkel

IPC: G11C29/08 ,  G11C11/16 ,  G11C7/00 ,  G11C5/14

CPC classification number: G11C11/1697 ,  G11C5/143 ,  G11C7/00 ,  G11C11/417 ,  G11C29/08 ,  G11C2207/2227

Abstract: A subsystem configured to select the power supply to a static random access memory cell compares the level of a dedicated memory supply voltage to the primary system supply voltage. The subsystem then switches the primary system supply to the SRAM cell when the system voltage is higher than the memory supply voltage with some margin. When the system voltage is lower than the memory supply voltage, with margin, the subsystem switches the memory supply to the SRAM cell. When the system voltage is comparable to the memory supply, the subsystem switches the system voltage to the SRAM cell if performance is a prioritized consideration, but switches the memory supply to the SRAM cell if power reduction is a prioritized consideration. In this manner, the system achieves optimum performance without incurring steady state power losses and avoids timing issues in accessing memory.

Abstract translation: 被配置为选择对静态随机存取存储器单元的电源的子系统将专用存储器电源电压的电平与主系统电源电压进行比较。 当系统电压高于具有一定余量的存储器电源电压时，子系统将主系统电源切换到SRAM单元。 当系统电压低于存储器电源电压时，子系统将存储器电源切换到SRAM单元。 当系统电压与存储器电源相当时，如果性能是优先考虑的话，子系统将系统电压切换到SRAM单元，但如果降低功耗是优先考虑的话，将存储器电源切换到SRAM单元。 以这种方式，系统实现最佳性能而不会导致稳态功率损耗，并避免访问存储器时的定时问题。

公开(公告)号：US09389622B2

公开(公告)日：2016-07-12

申请号：US14876332

申请日：2015-10-06

Applicant: Nvidia Corporation

Inventor： Brian L. Smith ,  Stephen Felix ,  Jesse Max Guss ,  Tezaswi Raja

IPC: G05F1/10 ,  G05F3/02 ,  G05F1/46

CPC classification number: G05F1/465 ,  G05F1/462

Abstract: A voltage margin controller, an IC included the same and a method of controlling voltage margin for a voltage domain of an IC are disclosed herein. In one embodiment, the voltage margin controller includes: (1) monitoring branches including circuit function indicators configured to indicate whether circuitry in the voltage domain could operate at corresponding candidate reduced voltage levels and (2) a voltage margin adjuster coupled to the monitoring branches and configured to develop a voltage margin adjustment for a voltage regulator of the voltage domain based upon an operating number of the circuit function indicators.

公开(公告)号：US09197365B2

公开(公告)日：2015-11-24

申请号：US13626606

申请日：2012-09-25

Applicant: Nvidia Corporation

Inventor： Stephen Felix ,  Dinkar Vasudevan ,  Steve Allpress

IPC: H04L1/00 ,  H04L1/18

CPC classification number: H04L1/005 ,  H04L1/1835

Abstract: Method, receiver and computer program product for decoding a coded data block received at the receiver are disclosed. A first plurality of coded data bits representing the coded data block are received. First soft information values are determined corresponding to respective ones of the received first plurality of coded data bits, wherein each of the soft information values indicates a likelihood of a corresponding coded data bit having a particular value. An attempt is made to decode the coded data block using the first soft information values. The first soft information values are compressed. The compressed first soft information values are stored in a data store. A second plurality of coded data bits representing the coded data block is received and second soft information values corresponding to respective ones of the received second plurality of coded data bits are determined. The compressed first soft information values are retrieved from the data store and decompressed. The decompressed first soft information values are combined with the second soft information values, and an attempt is made to decode the coded data block using the combined soft information values.

Abstract translation: 公开了用于解码在接收机处接收的编码数据块的方法，接收机和计算机程序产品。 接收表示编码数据块的第一多个编码数据位。 对应于接收到的第一多个编码数据位中的相应的第一个软信息值确定第一软信息值，其中每个软信息值指示具有特定值的对应编码数据位的似然性。 尝试使用第一软信息值对编码数据块进行解码。 第一个软信息值被压缩。 压缩的第一软信息值存储在数据存储器中。 接收表示编码数据块的第二多个编码数据比特，并且确定对应于所接收的第二多个编码数据比特中的相应数据比特的第二软信息值。 从数据存储中检索压缩的第一个软信息值并进行解压缩。 解压缩的第一软信息值与第二软信息值组合，并且尝试使用组合的软信息值对编码数据块进行解码。

公开(公告)号：US20150179232A1

公开(公告)日：2015-06-25

申请号：US14137859

申请日：2013-12-20

Applicant: NVIDIA Corporation

Inventor： Stephen Felix ,  Stéphane Badel

IPC: G11C5/14 ,  G11C11/419

CPC classification number: G11C5/145 ,  G11C5/14 ,  G11C8/16 ,  G11C11/412 ,  G11C11/417 ,  G11C11/419

Abstract: A method and a system are provided for performing memory access assist using voltage boost. A memory access request is received at a storage cell array that comprises two or more subarrays, each subarray including at least one row of storage cells. The voltage boost is applied, during the memory access, to a first negative supply voltage of a first storage cell subarray of the two or more storage cell subarrays. The first negative supply voltage of the first storage cell subarray is lower than a second negative supply voltage of a second storage cell subarray of the two or more storage cell subarrays.

Abstract translation: 提供了一种使用电压提升来执行存储器访问辅助的方法和系统。 在包含两个或更多个子阵列的存储单元阵列处接收存储器访问请求，每个子阵列包括至少一行存储单元。 在存储器访问期间将电压升高施加到两个或更多个存储单元子阵列的第一存储单元子阵列的第一负电源电压。 第一存储单元子阵列的第一负电源电压低于两个或多个存储单元子阵列的第二存储单元子阵列的第二负电源电压。

公开(公告)号：US20140086302A1

公开(公告)日：2014-03-27

申请号：US13626606

申请日：2012-09-25

Applicant: NVIDIA CORPORATION

Inventor： Stephen Felix ,  Dinkar Vasudevan ,  Steve Allpress

IPC: H04B1/66

CPC classification number: H04L1/005 ,  H04L1/1835

Abstract: Method, receiver and computer program product for decoding a coded data block received at the receiver are disclosed. A first plurality of coded data bits representing the coded data block are received. First soft information values are determined corresponding to respective ones of the received first plurality of coded data bits, wherein each of the soft information values indicates a likelihood of a corresponding coded data bit having a particular value. An attempt is made to decode the coded data block using the first soft information values. The first soft information values are compressed. The compressed first soft information values are stored in a data store. A second plurality of coded data bits representing the coded data block is received and second soft information values corresponding to respective ones of the received second plurality of coded data bits are determined. The compressed first soft information values are retrieved from the data store and decompressed. The decompressed first soft information values are combined with the second soft information values, and an attempt is made to decode the coded data block using the combined soft information values.

Abstract translation: 公开了用于解码在接收机处接收的编码数据块的方法，接收机和计算机程序产品。 接收表示编码数据块的第一多个编码数据位。 对应于接收到的第一多个编码数据位中的相应的第一个软信息值确定第一软信息值，其中每个软信息值指示具有特定值的对应编码数据位的似然性。 尝试使用第一软信息值对编码数据块进行解码。 第一个软信息值被压缩。 压缩的第一软信息值存储在数据存储器中。 接收表示编码数据块的第二多个编码数据比特，并且确定对应于所接收的第二多个编码数据比特中的相应数据比特的第二软信息值。 从数据存储中检索压缩的第一个软信息值并进行解压缩。 解压缩的第一软信息值与第二软信息值组合，并且尝试使用组合的软信息值对编码数据块进行解码。

公开(公告)号：US09766649B2

公开(公告)日：2017-09-19

申请号：US13947999

申请日：2013-07-22

Applicant: NVIDIA Corporation

Inventor： Stephen Felix ,  Jeffery Bond ,  Tezaswi Raja ,  Kalyana Bollapalli ,  Vikram Mehta

IPC: H03L1/00 ,  G06F1/08 ,  G06F1/32

CPC classification number: G06F1/08 ,  G06F1/324 ,  G06F1/3296 ,  H03L1/00 ,  Y02D10/126 ,  Y02D10/172

Abstract: A system is based on an IC. A first component of the IC generates a signal that clocks the IC at a target operating frequency. A period corresponding to the target clock frequency exceeds a duration of a longest critical path associated with the IC. The first component and synchronous logic of the IC clocked therewith, each functions with the core supply voltage, which may be supplied to each via the same power supply rail. A second IC component detects errors that relate to an operation of the IC at the target clock frequency and determines a level for adjusting the core supply voltage. The Vdd adjustment ameliorates the frequency error. The voltage determination uses closed loop dynamic voltage and frequency scaling.