公开(公告)号：US09123438B2

公开(公告)日：2015-09-01

申请号：US14054313

申请日：2013-10-15

Applicant: Nvidia Corporation

Inventor： Hwong-Kwo Lin ,  Lei Wang ,  Spencer Gold ,  Zhenye Jiang

IPC: G11C7/22 ,  G11C11/419 ,  G11C11/4076

CPC classification number: G11C11/419 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/417 ,  G11C29/022 ,  G11C29/028

Abstract: A configurable delay circuit and a method of clock buffering. One embodiment of the configurable delay circuit includes: (1) a first delay stage electrically couplable in series to a second delay stage, the first delay stage and the second delay stage each having an input port electrically coupled to a signal source, and (2) a delay path select circuit electrically coupled between the first delay stage and the second delay stage, and operable to select between a delay path including the first delay stage and another delay path including the first delay stage and the second delay stage.

Abstract translation: 可配置的延迟电路和时钟缓冲的方法。 可配置延迟电路的一个实施例包括：（1）与第二延迟级串联电耦合的第一延迟级，第一延迟级和第二延迟级各自具有电耦合到信号源的输入端，以及（2 ）电耦合在所述第一延迟级和所述第二延迟级之间的延迟路径选择电路，并且可操作以在包括所述第一延迟级的延迟路径和包括所述第一延迟级和所述第二延迟级的另一延迟路径之间进行选择。

公开(公告)号：US20150103584A1

公开(公告)日：2015-04-16

申请号：US14054313

申请日：2013-10-15

Applicant: Nvidia Corporation

Inventor： Hwong-Kwo Lin ,  Lei Wang ,  Spencer Gold ,  Zhenye Jiang

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/417 ,  G11C29/022 ,  G11C29/028

Abstract: A configurable delay circuit and a method of clock buffering. One embodiment of the configurable delay circuit includes: (1) a first delay stage electrically couplable in series to a second delay stage, the first delay stage and the second delay stage each having an input port electrically coupled to a signal source, and (2) a delay path select circuit electrically coupled between the first delay stage and the second delay stage, and operable to select between a delay path including the first delay stage and another delay path including the first delay stage and the second delay stage.

Abstract translation: 可配置的延迟电路和时钟缓冲的方法。 可配置延迟电路的一个实施例包括：（1）与第二延迟级串联电耦合的第一延迟级，第一延迟级和第二延迟级各自具有电耦合到信号源的输入端，以及（2 ）电耦合在所述第一延迟级和所述第二延迟级之间的延迟路径选择电路，并且可操作以在包括所述第一延迟级的延迟路径和包括所述第一延迟级和所述第二延迟级的另一延迟路径之间进行选择。

公开(公告)号：US09484115B1

公开(公告)日：2016-11-01

申请号：US14711712

申请日：2015-05-13

Applicant: NVIDIA CORPORATION

Inventor： Stephen Felix ,  Hwong-Kwo Lin ,  Spencer Gold ,  Jing Guo ,  Andreas Gotterba ,  Jason Golbus ,  Karthik Natarajan ,  Jun Yang ,  Zhenye Jiang ,  Ge Yang ,  Lei Wang ,  Yong Li ,  Hua Chen ,  Haiyan Gong ,  Beibei Ren ,  Eric Voelkel

IPC: G11C29/08 ,  G11C11/16 ,  G11C7/00 ,  G11C5/14

CPC classification number: G11C11/1697 ,  G11C5/143 ,  G11C7/00 ,  G11C11/417 ,  G11C29/08 ,  G11C2207/2227

Abstract: A subsystem configured to select the power supply to a static random access memory cell compares the level of a dedicated memory supply voltage to the primary system supply voltage. The subsystem then switches the primary system supply to the SRAM cell when the system voltage is higher than the memory supply voltage with some margin. When the system voltage is lower than the memory supply voltage, with margin, the subsystem switches the memory supply to the SRAM cell. When the system voltage is comparable to the memory supply, the subsystem switches the system voltage to the SRAM cell if performance is a prioritized consideration, but switches the memory supply to the SRAM cell if power reduction is a prioritized consideration. In this manner, the system achieves optimum performance without incurring steady state power losses and avoids timing issues in accessing memory.

Abstract translation: 被配置为选择对静态随机存取存储器单元的电源的子系统将专用存储器电源电压的电平与主系统电源电压进行比较。 当系统电压高于具有一定余量的存储器电源电压时，子系统将主系统电源切换到SRAM单元。 当系统电压低于存储器电源电压时，子系统将存储器电源切换到SRAM单元。 当系统电压与存储器电源相当时，如果性能是优先考虑的话，子系统将系统电压切换到SRAM单元，但如果降低功耗是优先考虑的话，将存储器电源切换到SRAM单元。 以这种方式，系统实现最佳性能而不会导致稳态功率损耗，并避免访问存储器时的定时问题。

公开(公告)号：US09390788B2

公开(公告)日：2016-07-12

申请号：US14809851

申请日：2015-07-27

Applicant: Nvidia Corporation

Inventor： Hwong-Kwo Lin ,  Lei Wang ,  Spencer Gold ,  Zhenye Jiang

IPC: G11C7/22 ,  G11C11/419 ,  G11C11/417 ,  G11C29/02 ,  G11C11/4076

CPC classification number: G11C11/419 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/417 ,  G11C29/022 ,  G11C29/028

Abstract: An SRAM clock circuit and an SRAM. In one embodiment, the SRAM clock circuit includes: (1) a plurality of transistor stacks optionally serially electrically couplable to form a configurable delay path through which a clock signal is buffered, and (2) a delay path select circuit respectively electrically coupled between pairs of the plurality of transistor stacks and operable to selectively electrically couple the plurality of transistor stacks to a base delay path, thereby activating the configurable delay path based on a desired delay.

Abstract translation: SRAM时钟电路和SRAM。 在一个实施例中，SRAM时钟电路包括：（1）多个晶体管堆叠，其可选地串联电耦合以形成缓冲时钟信号的可配置延迟路径;以及（2）延迟路径选择电路， 并且可操作以选择性地将多个晶体管堆叠电耦合到基本延迟路径，从而基于期望的延迟激活可配置的延迟路径。

公开(公告)号：US20150332757A1

公开(公告)日：2015-11-19

申请号：US14809851

申请日：2015-07-27

Applicant: Nvidia Corporation

Inventor： Hwong-Kwo Lin ,  Lei Wang ,  Spencer Gold ,  Zhenye Jiang

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/417 ,  G11C29/022 ,  G11C29/028

Abstract: An SRAM clock circuit and an SRAM. In one embodiment, the SRAM clock circuit includes: (1) a plurality of transistor stacks optionally serially electrically couplable to form a configurable delay path through which a clock signal is buffered, and (2) a delay path select circuit respectively electrically coupled between pairs of the plurality of transistor stacks and operable to selectively electrically couple the plurality of transistor stacks to a base delay path, thereby activating the configurable delay path based on a desired delay.

Abstract translation: SRAM时钟电路和SRAM。 在一个实施例中，SRAM时钟电路包括：（1）多个晶体管堆叠，其可选地串联电耦合以形成缓冲时钟信号的可配置延迟路径;以及（2）延迟路径选择电路， 并且可操作以选择性地将多个晶体管堆叠电耦合到基本延迟路径，从而基于期望的延迟激活可配置的延迟路径。