公开(公告)号：US11010323B2

公开(公告)日：2021-05-18

申请号：US16457287

申请日：2019-06-28

Applicant: NXP B.V.

Inventor： Gerrit Willem den Besten

IPC: G06F13/42 ,  G06F13/40

Abstract: An apparatus in various embodiments is for use in a local area network and includes a discernment logic circuit and logic circuitry. The discernment logic circuit discerns whether a requested communications transaction received over the management communications bus from another of the logic nodes involves a first type of transaction or a second type of transaction, the second type of transaction having a plurality of commands associated with the requested communications transaction to convey respectively different parts of the requested communications transaction including an address part and a data part. The logic circuitry disables, in response to a reset of an address pointer in the one of the plurality of logic nodes and the requested communications transaction being the second type of transaction, the address pointer to mitigate a likelihood that the requested communications transaction is performed via the communication protocol while the address pointer for the second type of transaction is erroneous.

公开(公告)号：US10284180B2

公开(公告)日：2019-05-07

申请号：US15619222

申请日：2017-06-09

Applicant: NXP B.V.

Inventor： Gerrit Willem den Besten

IPC: H03H17/02 ,  H04L25/03 ,  H04L25/06 ,  H03L7/08 ,  H04B1/10 ,  H04B1/16

Abstract: A circuit for correction of a signal which is susceptible to baseline wander. The circuit includes a front-end signal processing circuit, a slicer circuit, and a summing cross-over filter circuit. The front-end signal processing circuit includes a digital processing logic circuit and is used to process an input signal by mitigating signal artifacts. The slicer circuit samples the processed input signal and, therefrom, generates a symbol output derived from the sampled processed input signal. The summing cross-over filter circuit is arranged between the front-end signal processing circuit and the slicer circuit and mitigates baseline wander in the symbol output.

公开(公告)号：US08836408B1

公开(公告)日：2014-09-16

申请号：US13839687

申请日：2013-03-15

Applicant: NXP B.V.

Inventor： Gerrit Willem den Besten ,  Madan Vemula ,  Jingsong Zhou

IPC: H03K17/16 ,  H03K17/30

CPC classification number: H03K17/162 ,  H03K17/04163 ,  H03K17/693 ,  H03K2217/0018

Abstract: A data link circuit switches high-speed signals through FET-based circuitry between channels. A FET responds to control signals at the gate terminal to operate in either a signal-passing mode or another (blocking) mode. In the passing mode, an AC (high-speed) signal is passed between the S-D terminals by coupling a first signal portion (of the AC signal) and with another signal portion diverted by the inherent capacitances associated with the FET. For offsetting the loading caused by the inherent capacitances associated with the FET-based switch, a biasing circuit is configured and arranged to bias the back-gate terminal of the FET transistor with a follower signal.

Abstract translation: 数据链路电路通过通道之间的基于FET的电路切换高速信号。 FET响应于栅极端子处的控制信号，以信号传递模式或另一（阻塞）模式工作。 在通过模式中，通过耦合第一信号部分（AC信号）和与由FET相关联的固有电容转移的另一信号部分，在S-D端子之间通过AC（高速）信号。 为了抵消由与基于FET的开关相关联的固有电容引起的负载，偏置电路被配置和布置成用跟随器信号偏置FET晶体管的背栅极端子。

公开(公告)号：US20250125993A1

公开(公告)日：2025-04-17

申请号：US18828471

申请日：2024-09-09

Applicant: NXP B.V.

Inventor： Gerrit Willem den Besten ,  Philip Axer

IPC: H04L12/413 ,  H04L12/40

Abstract: A reconciliation module for a node of a multidrop bus network, the node comprising a MAC module and a PHY module, the reconciliation module comprising circuitry configured to: assert a sense signal until the beginning of each transmit opportunity of the node; de-assert the sense signal at that moment to cause the MAC module to send available data to the reconciliation module to start transmission of the data on the multidrop bus network via the PHY module at the respective transmit opportunity; and re-assert the sense signal on receipt of the data from the MAC module or time-out of the respective transmit opportunity.

公开(公告)号：US09025288B2

公开(公告)日：2015-05-05

申请号：US13835554

申请日：2013-03-15

Applicant: NXP B.V.

Inventor： Madan Vemula ,  James Caravella ,  James Spehar ,  Gerrit Willem den Besten

IPC: H02H9/00 ,  H02H9/04

CPC classification number: H02H9/041 ,  H02H9/046 ,  H03K17/693 ,  H03K2017/066 ,  H03K2217/0018

Abstract: Cross-talk is mitigated in a switching circuit. In accordance with one or more embodiments, an apparatus includes a multi-pin connector having signal-carrying electrodes that communicate with a device external to the apparatus, and respective field-effect switches that couple the signal-carrying electrodes to respective communication channels in the apparatus. The switches include a first field-effect semiconductor switch having a gate electrode adjacent a channel region that connects electrodes (e.g., source and drain regions) when a threshold switching voltage is applied to the gate, in which the electrodes are connected between one of the signal-carrying electrodes and a first channel coupled to an electrostatic discharge (ESD) circuit. A bias circuit mitigates cross-talk between the communication channels by biasing the channel region of the first field-effect semiconductor switch (in an off state) to boost the threshold switching voltage over a threshold discharge voltage of the ESD circuit.

Abstract translation: 串扰在开关电路中得到缓解。 根据一个或多个实施例，一种装置包括具有与设备外部的装置通信的信号承载电极的多针连接器以及将信号承载电极耦合到相应通信信道的相应的场效应开关 仪器。 开关包括第一场效应半导体开关，其具有栅极电极，邻近沟道区域，当阈值开关电压施加到栅极时，该栅极电极连接电极（例如，源极区域和漏极区域），其中电极连接在 信号承载电极和耦合到静电放电（ESD）电路的第一通道。 偏置电路通过偏置第一场效应半导体开关的通道区域（处于断开状态）来缓解通信通道之间的串扰，以提高阈值切换电压超过ESD电路的阈值放电电压。

公开(公告)号：US20140268445A1

公开(公告)日：2014-09-18

申请号：US13835554

申请日：2013-03-15

Applicant: NXP B.V.

Inventor： Madan Vemula ,  James Caravella ,  James Spehar ,  Gerrit Willem den Besten

IPC: H02H9/04

CPC classification number: H02H9/041 ,  H02H9/046 ,  H03K17/693 ,  H03K2017/066 ,  H03K2217/0018

Abstract: Cross-talk is mitigated in a switching circuit. In accordance with one or more embodiments, an apparatus includes a multi-pin connector having signal-carrying electrodes that communicate with a device external to the apparatus, and respective field-effect switches that couple the signal-carrying electrodes to respective communication channels in the apparatus. The switches include a first field-effect semiconductor switch having a gate electrode adjacent a channel region that connects electrodes (e.g., source and drain regions) when a threshold switching voltage is applied to the gate, in which the electrodes are connected between one of the signal-carrying electrodes and a first channel coupled to an electrostatic discharge (ESD) circuit. A bias circuit mitigates cross-talk between the communication channels by biasing the channel region of the first field-effect semiconductor switch (in an off state) to boost the threshold switching voltage over a threshold discharge voltage of the ESD circuit.

Abstract translation: 串扰在开关电路中得到缓解。 根据一个或多个实施例，一种装置包括具有与设备外部的装置通信的信号承载电极的多针连接器以及将信号承载电极耦合到相应通信信道的相应的场效应开关 仪器。 开关包括第一场效应半导体开关，其具有栅极电极，邻近沟道区域，当阈值开关电压施加到栅极时，该栅极电极连接电极（例如，源极区域和漏极区域），其中电极连接在 信号承载电极和耦合到静电放电（ESD）电路的第一通道。 偏置电路通过偏置第一场效应半导体开关的通道区域（处于断开状态）来缓解通信通道之间的串扰，以提高阈值切换电压超过ESD电路的阈值放电电压。

公开(公告)号：US20140266394A1

公开(公告)日：2014-09-18

申请号：US13839687

申请日：2013-03-15

Applicant: NXP B.V.

Inventor： Gerrit Willem den Besten ,  Madan Vemula ,  Jingsong Zhou

IPC: H03K17/16

CPC classification number: H03K17/162 ,  H03K17/04163 ,  H03K17/693 ,  H03K2217/0018

Abstract: A data link circuit switches high-speed signals through FET-based circuitry between channels. A FET responds to control signals at the gate terminal to operate in either a signal-passing mode or another (blocking) mode. In the passing mode, an AC (high-speed) signal is passed between the S-D terminals by coupling a first signal portion (of the AC signal) and with another signal portion diverted by the inherent capacitances associated with the FET. For offsetting the loading caused by the inherent capacitances associated with the FET-based switch, a biasing circuit is configured and arranged to bias the back-gate terminal of the FET transistor with a follower signal.

Abstract translation: 数据链路电路通过通道之间的基于FET的电路切换高速信号。 FET响应于栅极端子处的控制信号，以信号传递模式或另一（阻塞）模式工作。 在通过模式中，通过耦合第一信号部分（AC信号）和与由FET相关联的固有电容转移的另一信号部分，在S-D端子之间通过AC（高速）信号。 为了抵消由与基于FET的开关相关联的固有电容引起的负载，偏置电路被配置和布置成用跟随器信号偏置FET晶体管的背栅极端子。

公开(公告)号：US11500901B2

公开(公告)日：2022-11-15

申请号：US16456206

申请日：2019-06-28

Applicant: NXP B.V.

Inventor： Gerrit Willem den Besten

IPC: G06F16/27 ,  H04L61/00

Abstract: An apparatus for a local area network includes a management communications bus, and at one of a plurality of logic nodes, logic circuitry. The management communications bus is for communication among the plurality of logic nodes, wherein respective node addresses for the plurality of logic nodes are conveyed using the management communications bus. The logic circuitry communicates information in a data/address field of the communications protocol with another of the plurality of logic nodes with reference to a subset of the predetermined set of patterned data bits in the data/address field to synchronize the transactions.

公开(公告)号：US20180358953A1

公开(公告)日：2018-12-13

申请号：US15619222

申请日：2017-06-09

Applicant: NXP B.V.

Inventor： Gerrit Willem den Besten

IPC: H03H17/02 ,  H03L7/08 ,  H04B1/16 ,  H04B1/10

CPC classification number: H03H17/0219 ,  H03L7/0807 ,  H04B1/1036 ,  H04B1/16 ,  H04L25/03012 ,  H04L25/061 ,  H04L2025/0349

Abstract: A circuit for correction of a signal which is susceptible to baseline wander. The circuit includes a front-end signal processing circuit, a slicer circuit, and a summing cross-over filter circuit. The front-end signal processing circuit includes a digital processing logic circuit and is used to process an input signal by mitigating signal artifacts. The slicer circuit samples the processed input signal and, therefrom, generates a symbol output derived from the sampled processed input signal. The summing cross-over filter circuit is arranged between the front-end signal processing circuit and the slicer circuit and mitigates baseline wander in the symbol output.

公开(公告)号：US09467312B2

公开(公告)日：2016-10-11

申请号：US14202751

申请日：2014-03-10

Applicant: NXP B.V.

Inventor： Marcello Ganzerli ,  Gerrit Willem den Besten

IPC: H04L27/01 ,  H04L25/03

CPC classification number: H04L25/03057 ,  H04L25/03146 ,  H04L2025/03484 ,  H04L2025/0349

Abstract: Circuits, apparatus, and methods are disclosed for decision feedback equalization. In one embodiment, an apparatus includes a plurality of time-interleaved slices for processing an input data stream. Each of the slices includes a sampler circuit, a multiplexer, and a latch. In each slice, the multiplexer and the sampler circuit provide sampled output data corresponding to one of a plurality of different versions of the input data stream at times designated uniquely for the slice, according to one or more selection signals. The selection signals are derived from a output of the multiplexer of at least one other of the time-interleaved slices. The latch provides a controlled output in response to the multiplexer and the sampler circuit, as a function of the designated unique times.

Abstract translation: 公开了用于判决反馈均衡的电路，装置和方法。 在一个实施例中，一种装置包括用于处理输入数据流的多个时间交错切片。 每个片包括采样器电路，多路复用器和锁存器。 在每个切片中，多路复用器和采样器电路根据一个或多个选择信号提供对应于输入数据流的多个不同版本中的一个的采样输出数据，该时间是为片唯一地指定的。 选择信号从至少另一个时间交错切片的多路复用器的输出导出。 锁存器响应于多路复用器和采样器电路提供受控输出，作为指定的唯一时间的函数。