公开(公告)号：US5089869A

公开(公告)日：1992-02-18

申请号：US564087

申请日：1990-08-07

申请人： Naoto Matsuo ,  Shozo Okada ,  Michihiro Inoue

发明人： Naoto Matsuo ,  Shozo Okada ,  Michihiro Inoue

IPC分类号： H01L27/108

CPC分类号： H01L27/10817

摘要： Disclosed is a semiconductor memory device comprising a semiconductor substrate on which memory cells are formed, each including a switching transistor formed on the semiconductor substrate and a capacitor disposed above the switching transistor. The capacitor has a storage electrode, a cell plate and a capacitor insulating film sandwiched therebetween. The storage electrodes of at least two adjacent memory cells are partly disposed one above the other, with part of the cell plate interposed therebetween. Also disclosed is a semiconductor memory device in which the capacitors of the memory cells are disposed in a trench formed in the semiconductor substrate. The two switching transistors of two adjacent memory cells are located on each island-shaped active region surrounded by the trench. The storage electrodes of the capacitors of the two adjacent memory cells extend side by side around the corresponding active region, with part of the cell plate interposed between the storage electrodes.

摘要翻译： 公开了一种半导体存储器件，包括其上形成有存储单元的半导体衬底，每个半导体衬底包括形成在半导体衬底上的开关晶体管和设置在开关晶体管上方的电容器。 电容器具有夹在其间的存储电极，电池板和电容绝缘膜。 至少两个相邻的存储单元的存储电极被部分地设置在另一个之上，其中单元板的一部分插入其间。 还公开了一种半导体存储器件，其中存储单元的电容器设置在形成于半导体衬底中的沟槽中。 两个相邻存储器单元的两个开关晶体管位于由沟槽围绕的每个岛状有源区上。 两个相邻存储单元的电容器的存储电极围绕相应的有源区域并排延伸，其中一部分单元板插在存储电极之间。

公开(公告)号：US5316962A

公开(公告)日：1994-05-31

申请号：US926847

申请日：1992-08-06

申请人： Naoto Matsuo ,  Shozo Okada ,  Michihiro Inoue

发明人： Naoto Matsuo ,  Shozo Okada ,  Michihiro Inoue

IPC分类号： H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10841

摘要： A semiconductor memory device is provided which includes a semiconductor substrate of a first conductivity type, a plurality of trench capacitors formed in the substrate and a plurality of switching transistors formed on the respective trench capacitors. Each of the switching transistors is electrically connected to the corresponding trench capacitor. Each of the trench capacitors has a first electrode formed in the side portion of a trench provided in the substrate and a second electrode containing impurities of the first conductivity type and embedded in the trench. Each of the switching transistors has a source region formed from a first epitaxial layer of the first conductivity type grown on the trench so as to electrically contact the second electrode, a channel region formed from a second epitaxial layer of a second conductivity type grown on the first epitaxial layer, and a drain region formed from a third epitaxial layer of the first conductivity type grown on the second epitaxial layer. The first, second and third epitaxial layers are in contact with a polycrystalline silicon layer containing impurities of the second conductivity type. The first conductivity type is opposite to the second conductivity type.

摘要翻译： 提供了一种半导体存储器件，其包括第一导电类型的半导体衬底，形成在衬底中的多个沟槽电容器和形成在各个沟槽电容器上的多个开关晶体管。 每个开关晶体管电连接到相应的沟槽电容器。 每个沟槽电容器具有形成在设置在衬底中的沟槽的侧部中的第一电极和包含第一导电类型的杂质并且嵌入在沟槽中的第二电极。 每个开关晶体管具有由在沟槽上生长的第一导电类型的第一外延层形成的源区，以便与第二电极电接触，由第二导电类型生长的第二外延层形成的沟道区 第一外延层和由在第二外延层上生长的第一导电类型的第三外延层形成的漏极区。 第一，第二和第三外延层与含有第二导电类型杂质的多晶硅层接触。 第一导电类型与第二导电类型相反。

公开(公告)号：US5181089A

公开(公告)日：1993-01-19

申请号：US731420

申请日：1991-07-17

申请人： Naoto Matsuo ,  Shozo Okada ,  Michihiro Inoue

发明人： Naoto Matsuo ,  Shozo Okada ,  Michihiro Inoue

IPC分类号： H01L27/108

CPC分类号： H01L27/10841

摘要： A semiconductor memory device is provided which includes a semiconductor substrate of a first conductivity type, a plurality of trench capacitors formed in the substrate and a plurality of switching transistors formed on the respective trench capacitors. Each of the switching transistors is electrically connected to the corresponding trench capacitor. Each of the trench capacitors has a first electrode formed in the side portion of a trench provided in the substrate and a second electrode containing impurities of the first conductivity type and embedded in the trench. Each of the switching transistors has a source region formed from a first epitaxial layer of the first conductivity type grown on the trench so as to electrically contact the second electrode, a channel region formed from a second epitaxial layer of a second conductivity type grown on the first epitaxial layer, and a drain region formed from a third epitaxial layer of the first conductivity type grown on the second epitaxial layer. The first, second and third epitaxial layers are in contact with a polycrystalline silicon layer containing impurities of the second conductivity type. The first conductivity type is opposite to the second conductivity type.

摘要翻译： 提供了一种半导体存储器件，其包括第一导电类型的半导体衬底，形成在衬底中的多个沟槽电容器和形成在各个沟槽电容器上的多个开关晶体管。 每个开关晶体管电连接到相应的沟槽电容器。 每个沟槽电容器具有形成在设置在衬底中的沟槽的侧部中的第一电极和包含第一导电类型的杂质并且嵌入在沟槽中的第二电极。 每个开关晶体管具有由在沟槽上生长的第一导电类型的第一外延层形成的源区，以便与第二电极电接触，由第二导电类型生长的第二外延层形成的沟道区 第一外延层和由在第二外延层上生长的第一导电类型的第三外延层形成的漏极区。 第一，第二和第三外延层与含有第二导电类型杂质的多晶硅层接触。 第一导电类型与第二导电类型相反。

公开(公告)号：US5214296A

公开(公告)日：1993-05-25

申请号：US848840

申请日：1992-03-10

申请人： Yoshiro Nakata ,  Naoto Matsuo ,  Toshiki Yabu ,  Susumu Matsumoto ,  Shozo Okada

发明人： Yoshiro Nakata ,  Naoto Matsuo ,  Toshiki Yabu ,  Susumu Matsumoto ,  Shozo Okada

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/78642 ,  H01L27/10817

摘要： A thin-film semiconductor device having a vertical TFT which includes a gate insulating film formed on a sidewall of a throughhole formed in an insulating layer; a thin-film semiconductor layer formed on the gate insulating film; and a gate electrode formed within the insulating layer. The gate electrode, the gate insulating film, and the thin-film semiconductor layer together form a lateral MOS structure. The thin-film semiconductor layer is connected to a bit line at the bottom of the throughhole and to a storage node of a capacitor formed over the switching transistor.

摘要翻译： 一种具有垂直TFT的薄膜半导体器件，其包括形成在绝缘层中形成的通孔的侧壁上的栅极绝缘膜; 形成在所述栅极绝缘膜上的薄膜半导体层; 以及形成在所述绝缘层内的栅电极。 栅电极，栅极绝缘膜和薄膜半导体层一起形成横向MOS结构。 薄膜半导体层连接到通孔底部的位线和形成在开关晶体管上的电容器的存储节点。

公开(公告)号：US5399890A

公开(公告)日：1995-03-21

申请号：US257955

申请日：1994-06-10

申请人： Shozo Okada ,  Hisashi Ogawa ,  Naoto Matsuo ,  Yoshiro Nakata ,  Toshiki Yabu ,  Susumu Matsumoto

发明人： Shozo Okada ,  Hisashi Ogawa ,  Naoto Matsuo ,  Yoshiro Nakata ,  Toshiki Yabu ,  Susumu Matsumoto

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L27/105 ,  H01L27/10808

摘要： A semiconductor memory of the invention includes a semiconductor substrate having a plurality of transistors, a plurality of stacked capacitors connected to portions of the plurality of transistors, a plurality of first level interconnection layers connected to other portions of the plurality of transistors, and a plurality of second level interconnection layers disposed above the stacked capacitors and the first level interconnection layers. Each of the plurality of stacked capacitors includes a first electrode layer, a capacitance insulating film formed on top of the first electrode layer, and a second electrode layer formed on top of the capacitance insulating film. The second electrode layer is connected to a portion of one of the plurality of second level interconnection layers. At least portions of the plurality of first level interconnection layers are connected to other portions of the plurality of second level interconnection layers. Each of the plurality of first level interconnection layers shares the same layer as at least one of the first electrode layer and the second electrode layer.

摘要翻译： 本发明的半导体存储器包括具有多个晶体管的半导体衬底，与多个晶体管的一部分连接的多个叠层电容器，与多个晶体管的其它部分连接的多个第一级互连层，以及多个晶体管的多个 位于层叠电容器和第一级互连层之上的第二级互连层。 多个叠层电容器中的每一个包括第一电极层，形成在第一电极层顶部的电容绝缘膜，以及形成在电容绝缘膜顶部的第二电极层。 第二电极层连接到多个第二级互连层之一的一部分。 多个第一级互连层的至少一部分连接到多个第二级互连层的其它部分。 多个第一级互连层中的每一个与第一电极层和第二电极层中的至少一个共享相同的层。

公开(公告)号：US5217914A

公开(公告)日：1993-06-08

申请号：US683603

申请日：1991-04-10

申请人： Susumu Matsumoto ,  Toshiki Yabu ,  Yoshiro Nakata ,  Naoto Matsuo ,  Shozo Okada ,  Hiroyuki Sakai

发明人： Susumu Matsumoto ,  Toshiki Yabu ,  Yoshiro Nakata ,  Naoto Matsuo ,  Shozo Okada ,  Hiroyuki Sakai

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L27/10852 ,  H01L28/91

摘要： Disclosed is a semiconductor integrating circuit having stacked capacitor cells. Each of the cells includes an electric charge storage electrode for storing an electric charge, and a capacitor insulation film and opposite plate electrode integrated thereon. The electric charge storage electrode consists essentially of a bottom and a part in at least double frame-like portion or at least one column-like portion and at least one frame-like portion surrounding the column-like portion rising upwardly from the bottom surface. The capacitor deposited film consists of a dielectric material film deposited on all of the bottom plane and all surfaces of the charge storage electrode, and constructs a capacitor in cooperation with the opposite plate electrode. The described method for making a stacked capacitor cell can make it possible to form self-aligned capacitors by repeating a deposition of an oxide film and a conductive film and an anisotropic etching.

摘要翻译： 公开了具有层叠电容器单元的半导体积分电路。 每个单元包括用于存储电荷的电荷存储电极，以及集成在其上的电容器绝缘膜和相对的平板电极。 电荷存储电极基本上由至少双框状部分或至少一个柱状部分中的底部和部分组成，以及围绕从底面向上升起的柱状部分的至少一个框状部分。 电容器沉积膜由沉积在电荷存储电极的所有底面和所有表面上的介电材料膜构成，并与相对的板电极配合构建电容器。 所述制造叠层电容器电池的方法可以通过重复氧化膜和导电膜的沉积以及各向异性蚀刻来形成自对准电容器。

公开(公告)号：US5241201A

公开(公告)日：1993-08-31

申请号：US678150

申请日：1991-04-02

申请人： Naoto Matsuo ,  Shozo Okada ,  Susumu Matsumoto ,  Yoshiro Nakata ,  Toshiki Yabu

发明人： Naoto Matsuo ,  Shozo Okada ,  Susumu Matsumoto ,  Yoshiro Nakata ,  Toshiki Yabu

IPC分类号： H01L27/108

CPC分类号： H01L27/10817

摘要： A new semiconductor memory device for performing a read/write of information of randomly accessed address includes a plurality of memory cells put in parallel arrays. Each memory cell includes a switching transistor region and a capacitor region. The capacitor regions of the two adjacent memory cells are formed in a common region over the switching transistor region of the two adjacent memory cells. The charge storage electrode of the capacitor region has the shape of a loop. The charge storage electrodes are formed by using self-alignment.

摘要翻译： 用于执行随机访问地址的信息的读/写的新的半导体存储器件包括以并行阵列放置的多个存储单元。 每个存储单元包括开关晶体管区域和电容器区域。 两个相邻存储单元的电容器区域形成在两个相邻存储单元的开关晶体管区域上的公共区域中。 电容器区域的电荷存储电极具有环形。 电荷存储电极通过使用自对准形成。

公开(公告)号：US5315543A

公开(公告)日：1994-05-24

申请号：US882064

申请日：1992-05-12

申请人： Naoto Matsuo ,  Hisashi Ogawa ,  Yoshiro Nakata ,  Shozo Okada

发明人： Naoto Matsuo ,  Hisashi Ogawa ,  Yoshiro Nakata ,  Shozo Okada

IPC分类号： H01L27/108 ,  G11C13/00

CPC分类号： H01L27/10829

摘要： A semiconductor memory device includes a single crystalline semiconductor substrate having a main surface, a plurality of active regions formed at the main surface, and an isolation region which is formed at the main surface and isolates the active regions from one another. Each of the active regions has a transistor region and a capacitor region. The capacitor region has a trench formed in the single crystalline semiconductor substrate. An inner wall of the trench is covered with an insulating layer. At least a portion of the transistor region and the insulating layer are both covered with a semiconductor layer. A portion of the semiconductor layer which covers at least the portion of the transistor region is an epitaxial layer. A portion of the semiconductor layer which covers the insulating layer is a polycrystalline layer, which functions as a storage node of a capacitor. A semiconductor memory device is manufactured by forming an isolation region for isolating a plurality of active regions from one another at a main surface of a single crystalline semiconductor substrate, forming a trench in at least a portion of the active regions of the single crystalline semiconductor substrate, covering an inner wall of the trench with an insulating layer, forming a polysilicon seed film on the insulating layer, and growing a single crystalline silicon layer and a polysilicon layer respectively on an exposed portion of the top surface of the single crystalline semiconductor substrate and on the polysilicon seed film simultaneously and selectively.

摘要翻译： 半导体存储器件包括具有主表面，形成在主表面上的多个有源区的单晶半导体衬底和形成在主表面处的隔离区，并且将有源区彼此隔离。 每个有源区具有晶体管区和电容区。 电容器区域具有在单晶半导体衬底中形成的沟槽。 沟槽的内壁被绝缘层覆盖。 晶体管区域和绝缘层的至少一部分都被半导体层覆盖。 覆盖晶体管区域的至少一部分的半导体层的一部分是外延层。 覆盖绝缘层的半导体层的一部分是用作电容器的存储节点的多晶层。 半导体存储器件通过在单晶半导体衬底的主表面上形成用于隔离多个有源区彼此的隔离区域而形成，在单晶半导体衬底的至少一部分有源区中形成沟槽 用绝缘层覆盖沟槽的内壁，在绝缘层上形成多晶硅种子膜，分别在单晶半导体衬底的顶表面的暴露部分上生长单晶硅层和多晶硅层，以及 同时和选择性地在多晶硅种子膜上。

公开(公告)号：US5242852A

公开(公告)日：1993-09-07

申请号：US944883

申请日：1992-09-11

申请人： Kazuhiro Matsuyama ,  Masanori Fukumoto ,  Yasushi Naito ,  Hisashi Ogawa ,  Shozo Okada

发明人： Kazuhiro Matsuyama ,  Masanori Fukumoto ,  Yasushi Naito ,  Hisashi Ogawa ,  Shozo Okada

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242

CPC分类号： H01L27/10852 ,  H01L21/768 ,  H01L28/40 ,  Y10S438/908

摘要： In a method for manufacturing DRAMs in a stacked memory cell type, an edge portion of each bit line is bared upon etching a first insulating film, the bared edge portion is etched to from an opening and an inner peripheral surface of the opening is covered by a second insulating film. There is also disclosed a method wherein second and third insulating films and second conductive film are stacked on a first insulating film, a second conductive film is formed and the second conductive film and the first conductive film are partially etched whereby the unetched portions of the first conductive film serve as electrode planes of charge storage electrodes.

摘要翻译： 在以堆叠式存储单元型制造DRAM的方法中，蚀刻第一绝缘膜时，每个位线的边缘部分被露出，裸露的边缘部分被从开口蚀刻并且开口的内周面被 第二绝缘膜。 还公开了一种方法，其中第二绝缘膜和第三绝缘膜和第二导电膜堆叠在第一绝缘膜上，形成第二导电膜，并且第二导电膜和第一导电膜被部分蚀刻，由此第一绝缘膜的未蚀刻部分 导电膜用作电荷存储电极的电极平面。

公开(公告)号：US5182452A

公开(公告)日：1993-01-26

申请号：US776852

申请日：1991-10-15

申请人： Masaaki Niwa ,  Shozo Okada

发明人： Masaaki Niwa ,  Shozo Okada

IPC分类号： G01Q60/10 ,  H01J37/00 ,  H01J37/30

CPC分类号： G01Q60/16 ,  B82Y35/00 ,  Y10S977/854

摘要： There is provided a method for determining the presence of an insulating film on the surface of an electrically conductive material. In this method, an electrically conductive probe is brought into contact with the surface of a specimen, and a voltage is applied between the probe and the surface of the specimen. A tunneling current which flows through the probe is detected and amplified, while controlling the distance between the probe and the surface of the specimen to ensure a substantially constant tunneling current.

摘要翻译： 提供了一种用于确定在导电材料的表面上存在绝缘膜的方法。 在该方法中，使导电探针与试样的表面接触，并且在探针与试样的表面之间施加电压。 检测并放大流过探针的隧穿电流，同时控制探针与样品表面之间的距离，以确保基本上恒定的隧道电流。