公开(公告)号：US20160181376A1

公开(公告)日：2016-06-23

申请号：US15058139

申请日：2016-03-01

Applicant: FUJI ELECTRIC CO., LTD. ,  NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY

Inventor： Makoto UTSUMI ,  Yoshiyuki SAKAI ,  Kenji FUKUDA ,  Shinsuke HARADA ,  Mitsuo OKAMOTO

IPC: H01L29/16 ,  H01L29/45 ,  H01L21/283 ,  H01L21/324 ,  H01L29/66 ,  H01L21/04

CPC classification number: H01L29/1608 ,  H01L21/0485 ,  H01L21/283 ,  H01L21/324 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/66477 ,  H01L29/7802

Abstract: An infrared ray absorbing film is selectively formed on a surface of a silicon carbide semiconductor substrate in a predetermined area. An aluminum film and a nickel film are sequentially formed in this order on the silicon carbide semiconductor substrate in an area excluding the predetermined area in which the infrared ray absorbing film is formed. The silicon carbide semiconductor substrate is thereafter heated using a rapid annealing process with a predetermined heating rate to form an electrode. The rapid annealing process converts the nickel film into a silicide and, with the aluminum film, provides an electrode having ohmic contact.

Abstract translation: 选择性地在预定区域的碳化硅半导体衬底的表面上形成红外线吸收膜。 在除了形成有红外线吸收膜的预定区域之外的区域中，在碳化硅半导体衬底上依次形成铝膜和镍膜。 然后用预定加热速率的快速退火工艺加热碳化硅半导体衬底以形成电极。 快速退火工艺将镍膜转化成硅化物，并且与铝膜一起提供具有欧姆接触的电极。

公开(公告)号：US20160126092A1

公开(公告)日：2016-05-05

申请号：US14991887

申请日：2016-01-08

Applicant: FUJI ELECTRIC CO., LTD. ,  NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY

Inventor： Youichi MAKIFUCHI ,  Takashi TSUTSUMI ,  Tsuyoshi ARAOKA ,  Mitsuo OKAMOTO ,  Kenji FUKUDA

IPC: H01L21/02 ,  H01L29/51 ,  H01L29/16

CPC classification number: H01L21/02337 ,  H01L21/049 ,  H01L29/1608 ,  H01L29/51 ,  H01L29/518 ,  H01L29/78 ,  H01L29/94

Abstract: On a silicon carbide semiconductor substrate, heat treatment is performed after one layer or two or more layers of an oxide film, a nitride film, or an oxynitride film are formed as a gate insulating film. The heat treatment after the gate insulating film is formed is performed for a given period in an atmosphere that includes H2 and H2O without including O2. As a result, hydrogen or hydroxyl groups can be segregated in a limited region that includes the interface of the silicon carbide substrate and the gate insulating film. The width of the region to which the hydrogen or hydroxyl groups is segregated is from 0.5 nm to 10 nm. In such a manner, the interface state density can be lowered and high channel mobility can be realized.

Abstract translation: 在碳化硅半导体衬底上，在形成一层或两层或更多层氧化膜，氮化物膜或氧氮化物膜作为栅极绝缘膜之后进行热处理。 形成栅极绝缘膜之后的热处理在包括H 2和H 2 O但不包括O 2的气氛中进行规定的时间。 结果，氢或羟基可以在包括碳化硅衬底和栅极绝缘膜的界面的有限区域中分离。 氢或羟基分离的区域的宽度为0.5nm至10nm。 以这种方式，可以降低界面状态密度并且可以实现高通道迁移率。

公开(公告)号：US20160336224A1

公开(公告)日：2016-11-17

申请号：US15221678

申请日：2016-07-28

Applicant: FUJI ELECTRIC CO., LTD. ,  NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY

Inventor： Yoshiyuki SUGAHARA ,  Takashi TSUTSUMI ,  Youichi MAKIFUCHI ,  Tsuyoshi ARAOKA ,  Kenji FUKUDA ,  Shinsuke HARADA ,  Mitsuo OKAMOTO

IPC: H01L21/768 ,  H01L23/532 ,  H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L29/10

CPC classification number: H01L21/76883 ,  H01L21/045 ,  H01L21/0485 ,  H01L21/049 ,  H01L21/28 ,  H01L21/76846 ,  H01L23/53223 ,  H01L29/1095 ,  H01L29/12 ,  H01L29/1608 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7802

Abstract: A method of manufacturing a silicon carbide semiconductor device includes forming on a front surface of a silicon carbide substrate of a first conductivity type, a silicon carbide layer of the first conductivity type of a lower concentration; selectively forming a region of a second conductivity type in a surface portion of the silicon carbide layer; selectively forming a source region of the first conductivity type in the region; forming a source electrode electrically connected to the source region; forming a gate insulating film on a surface of the region between the silicon carbide layer and the source region; forming a gate electrode on the gate insulating film; forming a drain electrode on a rear surface of the substrate; forming metal wiring comprising aluminum for the device, the metal wiring being connected to the source electrode; and performing low temperature nitrogen annealing after the metal wiring is formed.

Abstract translation: 一种制造碳化硅半导体器件的方法包括在第一导电类型的碳化硅衬底的前表面上形成较低浓度的第一导电类型的碳化硅层; 在碳化硅层的表面部分中选择性地形成第二导电类型的区域; 在该区域中选择性地形成第一导电类型的源区; 形成与源极电连接的源电极; 在所述碳化硅层和所述源极区域之间的区域的表面上形成栅极绝缘膜; 在栅极绝缘膜上形成栅电极; 在所述基板的后表面上形成漏电极; 形成用于所述器件的铝的金属布线，所述金属布线连接到所述源电极; 并且在形成金属布线之后进行低温氮退火。

公开(公告)号：US20250089356A1

公开(公告)日：2025-03-13

申请号：US18926357

申请日：2024-10-25

Applicant: National Institute of Advanced Industrial Science and Technology

Inventor： Atsushi YAO ,  Mitsuo OKAMOTO ,  Fumiki KATO ,  Hiroshi SATO ,  Shinsuke HARADA ,  Hiroshi HOZOJI ,  Shinji SATO

IPC: H01L27/092 ,  H01L23/522 ,  H01L25/065 ,  H01L29/16 ,  H03K17/0412

Abstract: A change in switching time due to temperature change is suppressed. A switching circuitry is provided with a resistance component having opposite characteristics to temperature dependence of a gate current of a power transistor which is switching-controlled by the switching circuitry, and a change in a gate current due to the temperature change is suppressed by a change in the above-described resistance component due to the temperature change.

公开(公告)号：US20240266351A1

公开(公告)日：2024-08-08

申请号：US18563937

申请日：2022-04-28

Applicant: National Institute of Advanced Industrial Science and Technology

Inventor： Mitsuo OKAMOTO ,  Atsushi YAO ,  Hiroshi SATO ,  Shinsuke HARADA

IPC: H01L27/092 ,  H01L21/04 ,  H01L21/82 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0922 ,  H01L21/0465 ,  H01L21/049 ,  H01L21/8213 ,  H01L29/063 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7813 ,  H01L29/7816

Abstract: A semiconductor device includes, on an n-type semiconductor substrate, a power transistor, an n-type transistor, and a p-type transistor on a laminated semiconductor substrate that laminates an n-type drift layer, a p-type; the power transistor has a trench gate electrode penetrating through the base layer; the p-type transistor is formed in an n-type well region formed in the base layer, and the n-type transistor is formed in a p-type well region further formed in the base layer or n-type well region; and a p-type impurity concentration of the buried channel region of the p-type transistor is equal to a p-type impurity concentration of the base layer.