公开(公告)号：US20250089356A1

公开(公告)日：2025-03-13

申请号：US18926357

申请日：2024-10-25

Applicant: National Institute of Advanced Industrial Science and Technology

Inventor： Atsushi YAO ,  Mitsuo OKAMOTO ,  Fumiki KATO ,  Hiroshi SATO ,  Shinsuke HARADA ,  Hiroshi HOZOJI ,  Shinji SATO

IPC: H01L27/092 ,  H01L23/522 ,  H01L25/065 ,  H01L29/16 ,  H03K17/0412

Abstract: A change in switching time due to temperature change is suppressed. A switching circuitry is provided with a resistance component having opposite characteristics to temperature dependence of a gate current of a power transistor which is switching-controlled by the switching circuitry, and a change in a gate current due to the temperature change is suppressed by a change in the above-described resistance component due to the temperature change.

公开(公告)号：US20240332281A1

公开(公告)日：2024-10-03

申请号：US18737031

申请日：2024-06-07

Applicant: National Institute of Advanced Industrial Science and Technology

Inventor： Akira NAKAJIMA ,  Shinsuke HARADA ,  Kazutoshi KOJIMA

IPC: H01L27/02 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L27/0255 ,  H01L29/2003 ,  H01L29/7786

Abstract: A destructive breakdown mode that leads to the destruction of a device is suppressed, in the case where a gallium nitride-based high electron mobility transistor is used as a power device. A diode is connected in antiparallel to a HEMT, and this antiparallel connected diode is designed such that an avalanche breakdown occurs therein before the drain-source voltage, which is the difference between the drain potential applied to a drain electrode and the source potential applied to a source electrode, exceeds the withstand voltage of the HEMT.

公开(公告)号：US20240266351A1

公开(公告)日：2024-08-08

申请号：US18563937

申请日：2022-04-28

Applicant: National Institute of Advanced Industrial Science and Technology

Inventor： Mitsuo OKAMOTO ,  Atsushi YAO ,  Hiroshi SATO ,  Shinsuke HARADA

IPC: H01L27/092 ,  H01L21/04 ,  H01L21/82 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0922 ,  H01L21/0465 ,  H01L21/049 ,  H01L21/8213 ,  H01L29/063 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7813 ,  H01L29/7816

Abstract: A semiconductor device includes, on an n-type semiconductor substrate, a power transistor, an n-type transistor, and a p-type transistor on a laminated semiconductor substrate that laminates an n-type drift layer, a p-type; the power transistor has a trench gate electrode penetrating through the base layer; the p-type transistor is formed in an n-type well region formed in the base layer, and the n-type transistor is formed in a p-type well region further formed in the base layer or n-type well region; and a p-type impurity concentration of the buried channel region of the p-type transistor is equal to a p-type impurity concentration of the base layer.

公开(公告)号：US20140113421A1

公开(公告)日：2014-04-24

申请号：US14145147

申请日：2013-12-31

Applicant: SANYO ELECTRIC CO., LTD. ,  NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY

Inventor： Shinsuke HARADA ,  Tsutomu Yatsuo ,  Kenji Fukuda ,  Mitsuo Okamoto ,  Kazuhiro Adachi ,  Seiji Suzuki

IPC: H01L29/66 ,  H01L21/02

CPC classification number: H01L29/66477 ,  H01L21/02529 ,  H01L21/0465 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/7802

Abstract: A silicon carbide vertical MOSFET having low ON-resistance and high blocking voltage is provided. For this, a first deposition film (2) of low concentration silicon carbide of a first conductivity type is formed on the surface of a high concentration silicon carbide substrate (1) of a first conductivity type. Formed on the first deposition film (2) is a second deposition film (31) that comprises a high concentration gate region of a second conductivity type, with a first region removed selectively. A third deposition film (32) formed on the second deposition film, which comprises a second region that is wider than the selectively removed first region, a high concentration source region (5) of a first conductivity type and a low concentration gate region (11) of a second conductivity type. A low concentration base region (4) of a first conductivity type is formed in contact with the first deposition film (2) in the first and second regions.

Abstract translation: 提供具有低导通电阻和高阻断电压的碳化硅垂直MOSFET。 为此，在第一导电类型的高浓度碳化硅衬底（1）的表面上形成第一导电类型的低浓度碳化硅的第一沉积膜（2）。 形成在第一沉积膜（2）上的是第二沉积膜（31），其包括第二导电类型的高浓度栅极区域，其中第一区域被选择性地去除。 形成在第二沉积膜上的第三沉积膜（32）包括比选择性去除的第一区域宽的第二区域，第一导电类型和低浓度栅极区域（11）的高浓度源区域（5） ）第二导电类型。 在第一和第二区域中形成与第一沉积膜（2）接触的第一导电类型的低浓度基区（4）。

公开(公告)号：US20180358463A1

公开(公告)日：2018-12-13

申请号：US15993708

申请日：2018-05-31

Applicant: FUJI ELECTRIC CO., LTD. ,  NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY

Inventor： Yusuke KOBAYASHI ,  Naoyuki OHSE ,  Shinsuke HARADA ,  Manabu TAKEI

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/16 ,  H01L29/47

CPC classification number: H01L29/7813 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/47 ,  H01L29/7806

Abstract: On a front surface of a semiconductor base, a first n−-type drift region and a second n-type drift region are provided. A gate trench is provided that penetrates an n+-type source region and p-type base region, and reaches the second n-type drift region. Between adjacent gate trenches, a contact trench is provided that penetrates the n+-type source region and the p-type base region, and reaches a p-type semiconductor region, through the second n-type drift region. A source electrode embedded in the contact trench is in contact with the p-type semiconductor region at a bottom and corners of the contact trench, and forms a Schottky junction with the second n-type drift region at side walls of the contact trench. A depth of the contact trench is a depth by which a mathematical area of a part thereof forming the Schottky junction is a predetermined mathematical area or greater.

公开(公告)号：US20160181376A1

公开(公告)日：2016-06-23

申请号：US15058139

申请日：2016-03-01

Applicant: FUJI ELECTRIC CO., LTD. ,  NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY

Inventor： Makoto UTSUMI ,  Yoshiyuki SAKAI ,  Kenji FUKUDA ,  Shinsuke HARADA ,  Mitsuo OKAMOTO

IPC: H01L29/16 ,  H01L29/45 ,  H01L21/283 ,  H01L21/324 ,  H01L29/66 ,  H01L21/04

CPC classification number: H01L29/1608 ,  H01L21/0485 ,  H01L21/283 ,  H01L21/324 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/66477 ,  H01L29/7802

Abstract: An infrared ray absorbing film is selectively formed on a surface of a silicon carbide semiconductor substrate in a predetermined area. An aluminum film and a nickel film are sequentially formed in this order on the silicon carbide semiconductor substrate in an area excluding the predetermined area in which the infrared ray absorbing film is formed. The silicon carbide semiconductor substrate is thereafter heated using a rapid annealing process with a predetermined heating rate to form an electrode. The rapid annealing process converts the nickel film into a silicide and, with the aluminum film, provides an electrode having ohmic contact.

Abstract translation: 选择性地在预定区域的碳化硅半导体衬底的表面上形成红外线吸收膜。 在除了形成有红外线吸收膜的预定区域之外的区域中，在碳化硅半导体衬底上依次形成铝膜和镍膜。 然后用预定加热速率的快速退火工艺加热碳化硅半导体衬底以形成电极。 快速退火工艺将镍膜转化成硅化物，并且与铝膜一起提供具有欧姆接触的电极。

公开(公告)号：US20240213364A1

公开(公告)日：2024-06-27

申请号：US18556293

申请日：2022-04-15

Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY

Inventor： Yoshinao MIURA ,  Akira NAKAJIMA ,  Xu-Qiang SHEN ,  Hirohisa HIRAI ,  Shinsuke HARADA

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/20 ,  H01L29/861

CPC classification number: H01L29/7811 ,  H01L21/265 ,  H01L29/2003 ,  H01L29/7813 ,  H01L29/8613

Abstract: There is provided a semiconductor equipment including: an element area having an n-type layer, a first p-type layer on the n-type layer, and a second p-type layer on the first p-type layer, the second p-type layer having an acceptor concentration higher than the first p-type layer; and an electric field relaxation region surrounding the element area, in which in the electric field relaxation region, a region containing an impurity element that inactivates a part of acceptors in the first p-type layer and the second p-type layer is provided in the first p-type layer and the second p-type layer.

公开(公告)号：US20230246102A1

公开(公告)日：2023-08-03

申请号：US18297559

申请日：2023-04-07

Applicant: FUJI ELECTRIC CO., LTD. ,  NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY

Inventor： Naoki KUMAGAI ,  Masakazu OKADA ,  Shinsuke HARADA

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/06

CPC classification number: H01L29/7811 ,  H01L29/1608 ,  H01L29/0638 ,  H01L29/0696

Abstract: A superjunction semiconductor device having a termination structure portion surrounding an active region in a plan view. The device includes: a semiconductor substrate; a first semiconductor layer provided on the semiconductor substrate; and a parallel pn structure and a channel stopper provided in the first semiconductor layer. The channel stopper surrounds the parallel pn structure in the plan view, and contacts the parallel pn structure in the termination structure portion. The parallel pn structure includes a plurality of first columns each having a first width and a plurality of second columns each having a second width that repeatedly alternate one another parallel to the main surface. In a region of the parallel pn structure contacting the channel stopper, a product of the second width and an impurity concentration of the second columns is less than a product of the first width and an impurity concentration of the first columns.

公开(公告)号：US20210183995A1

公开(公告)日：2021-06-17

申请号：US17186881

申请日：2021-02-26

Applicant: FUJI ELECTRIC CO., LTD. ,  NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY ,  KABUSHIKI KAISHA TOSHIBA

Inventor： Yusuke KOBAYASHI ,  Manabu TAKEI ,  Shinya KYOGOKU ,  Shinsuke HARADA

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

Abstract: A superjunction silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a parallel pn structure in which epitaxially grown first column regions of the first conductivity type and ion-implanted second column regions of a second conductivity type are disposed to repeatedly alternate with one another, a second semiconductor layer of the second conductivity type, first semiconductor regions of the first conductivity type, trenches, gate electrodes provided in the trenches via gate insulating films, another electrode, and a third semiconductor layer of the first conductivity type. The first column regions have an impurity concentration in a range from 1.1×1016/cm3 to 5.0×1016/cm3.

公开(公告)号：US20170110571A1

公开(公告)日：2017-04-20

申请号：US15252623

申请日：2016-08-31

Applicant: FUJI ELECTRIC CO., LTD. ,  NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY

Inventor： Yusuke KOBAYASHI ,  Manabu TAKEI ,  Shinsuke HARADA

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/16

CPC classification number: H01L29/7813 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7839

Abstract: In a front surface of a semiconductor base body, a gate trench is disposed penetrating an n+-type source region and a p-type base region to a second n-type drift region. In the second n-type drift region, a p-type semiconductor region is selectively disposed. Between adjacent gate trenches, a contact trench is disposed penetrating the n+-type source region and the p-type base region, and going through the second n-type drift region to the p-type semiconductor region. A source electrode embedded in the contact trench contacts the p-type semiconductor region at a bottom portion and corner portion of the contact trench, and forms a Schottky junction with the second n-type drift region at a side wall of the contact trench.