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    Method of manufacturing semiconductor device having interconnection layer contacting source/drain regions
    1.
    发明授权
    Method of manufacturing semiconductor device having interconnection layer contacting source/drain regions 失效
    制造具有接触源极/漏极区域的互连层的半导体器件的方法

    公开(公告)号：US5240872A

    公开(公告)日：1993-08-31

    申请号：US925148

    申请日：1992-08-06

    申请人： Kaoru Motonami ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yoshinori Okumura ,  Yasushi Matsui

    发明人： Kaoru Motonami ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yoshinori Okumura ,  Yasushi Matsui

    IPC分类号： H01L21/8242 ,  H01L23/485 ,  H01L27/108

    CPC分类号： H01L27/10873 ,  H01L23/485 ,  H01L27/10817 ,  H01L2924/0002

    摘要： A semiconductor device includes a MOS type field effect transistor whose gate electrode (4) has its surface covered with a first insulating film (5) and left and right sides provided with a pair of second insulating films (10). A first conductive layer (12, 13) is formed on the surface of the source/drain region (8, 11) and the surface of one of a pair of second insulating films (10) which are positioned on one side of the gate electrode (4). A third insulating film (24b) is formed at least on the surface of the second insulating film (10) on which the first conductive layer (12, 13) is not formed. A second conductive layer (18) is provided on the surface of the third insulating film (24b) and on the source/drain region (8, 11) on which the third insulating film (24b) is formed. This structure enables provision of a semiconductor device in which a contact hole can be formed in self-alignment, independent from the influence of errors in the step of patterning a resist mask.

    摘要翻译： 半导体器件包括MOS型场效应晶体管，其栅极（4）的表面被第一绝缘膜（5）覆盖，左右侧设置有一对第二绝缘膜（10）。 第一导电层（12,13）形成在源/漏区（8,11）的表面上，并且一对第二绝缘膜（10）中的一个位于栅电极的一侧的表面 （4）。 至少在没有形成第一导电层（12,13）的第二绝缘膜（10）的表面上形成第三绝缘膜（24b）。 在第三绝缘膜（24b）的表面和形成有第三绝缘膜（24b）的源/漏区（8,11）上设置第二导电层（18）。 该结构能够提供可以独立于图案化抗蚀剂掩模的步骤中的误差的影响的自对准中形成接触孔的半导体器件。

    Semiconductor device having interconnection layer contacting source/drain regions
    2.
    发明授权
    Semiconductor device having interconnection layer contacting source/drain regions 失效
    具有互连层的半导体器件接触源/漏区

    公开(公告)号：US5173752A

    公开(公告)日：1992-12-22

    申请号：US690824

    申请日：1991-04-26

    申请人： Kaoru Motonami ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yoshinori Okumura ,  Yasushi Matsui

    发明人： Kaoru Motonami ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yoshinori Okumura ,  Yasushi Matsui

    IPC分类号： H01L27/10 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L23/522 ,  H01L27/108 ,  H01L29/417 ,  H01L29/78

    CPC分类号： H01L27/10873 ,  H01L23/485 ,  H01L27/10817 ,  H01L2924/0002 ,  Y10S257/90

    摘要： A semiconductor device incloudes a MOS type field effect transistor whose gate electrode (4) has its surface covered with a first insulating film (5) and left and right sides provided with a pair of second insulating films (10). A first conductive layer (12, 13) is formed on the surface of the source/drain region (8, 11) and the surface of one of a pair of second insulating films (10) which are positioned on one side of the gate electrode (4). A third insulating film (24b) is formed at least on the surface of the second insulating film (10) on which the first conductive layer (12, 13) is not formed. A second conductive layer (18) is provided on the surface of the third insulating film (24b) and on the source/drain region (8, 11) on which the third insulating film (24b) is formed. This structure enables provision of a semiconductor device in which a contact hole can be formed in self-alignment, independent from the influence of errors in the step of patterning a resist mask.

    摘要翻译： 半导体器件包括MOS型场效应晶体管，其栅电极（4）的表面被第一绝缘膜（5）覆盖，左侧和右侧设置有一对第二绝缘膜（10）。 第一导电层（12,13）形成在源/漏区（8,11）的表面上，并且一对第二绝缘膜（10）中的一个位于栅电极的一侧的表面 （4）。 至少在没有形成第一导电层（12,13）的第二绝缘膜（10）的表面上形成第三绝缘膜（24b）。 在第三绝缘膜（24b）的表面和形成有第三绝缘膜（24b）的源/漏区（8,11）上设置第二导电层（18）。 该结构能够提供可以独立于图案化抗蚀剂掩模的步骤中的误差的影响的自对准中形成接触孔的半导体器件。

    Method of making a semiconductor integrated device having gate sidewall structure
    3.
    发明授权
    Method of making a semiconductor integrated device having gate sidewall structure 失效
    制造具有栅极侧壁结构的半导体集成器件的方法

    公开(公告)号：US5338699A

    公开(公告)日：1994-08-16

    申请号：US10691

    申请日：1993-01-29

    申请人： Makoto Ohi ,  Hideaki Arima ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yasushi Matsui

    发明人： Makoto Ohi ,  Hideaki Arima ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yasushi Matsui

    IPC分类号： H01L27/04 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L27/10852 ,  H01L21/76801 ,  H01L21/76834 ,  H01L27/10808 ,  Y10S257/90

    摘要： A method of making a semiconductor device including a plurality of gate electrodes (6a, 6b, 6c, 6d) arranged on the surface of a semiconductor substrate (1) with insulating layers (5, 8) covering the top and the side walls of the gate electrodes. The spaces between the opposing side walls of adjacent gate electrodes on the surface of the element isolation region (2) are smaller than twice the thickness of the thinnest insulating layer (8) among the insulating layers of the side walls of the gate electrodes on the surface of the active regions. The space (14) between the gate electrodes on the element isolation region is filled with the insulating isolation layer (8) so that unevenness in the underlying portion on the element isolation region on which the conductive interconnection layer (10) to be formed is reduced, preventing thinning of the conductive interconnection layer and disconnection due to excessive etching of a resist film in patterning the conductive interconnection layer.

    摘要翻译： 一种制造半导体器件的方法，该半导体器件包括布置在半导体衬底（1）的表面上的多个栅电极（6a，6b，6c，6d），绝缘层（5,8）覆盖了顶部和侧壁 栅电极。 元件隔离区域（2）表面上的相邻栅电极的相对侧壁之间的间隔小于栅电极侧壁绝缘层中最薄绝缘层（8）的厚度的两倍 活性区的表面。 元件隔离区域上的栅电极之间的空间（14）填充有绝缘隔离层（8），使得要形成导电互连层（10）的元件隔离区域上的下面部分的不均匀性减小 防止导电互连层变薄，并且在图案化导电互连层时由于抗蚀剂膜的过度蚀刻而导致的断开。

    Semiconductor device having gate electrode spacing dependent upon gate side wall insulating dimension
    4.
    发明授权
    Semiconductor device having gate electrode spacing dependent upon gate side wall insulating dimension 失效
    具有栅极电极间距的半导体器件与栅极侧壁绝缘尺寸相关

    公开(公告)号：US5233212A

    公开(公告)日：1993-08-03

    申请号：US692395

    申请日：1991-04-25

    申请人： Makoto Ohi ,  Hideaki Arima ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yasushi Matsui

    发明人： Makoto Ohi ,  Hideaki Arima ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yasushi Matsui

    IPC分类号： H01L27/04 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

    CPC分类号： H01L27/10852 ,  H01L21/76801 ,  H01L21/76834 ,  H01L27/10808 ,  Y10S257/90

    摘要： A semiconductor device includes a plurality of gate electrodes (6a, 6b, 6c, 6d) arranged on the surface of a semiconductor substrate (1) with insulating layers (5, 8) covering the top and the side walls of the gate electrodes. The spaces between the opposing side walls of adjacent gate electrodes on the surface of the element isolation region (2) re smaller than twice the thickness of the thinnest insulating layer (8) among the insulating layers of the side walls of the gate electrodes on the surface of the active regions. The space (14) between the gate electrodes on the element isolation region is filled with the insulating isolation layer (8) so that unevenness in the underlying portion on the element isolation region on which the conductive interconnection layer (10) to be formed is reduced, preventing thinning of the conductive interconnection layer and disconnection due to excessive etching of a resin film in patterning the conductive interconnection layer.

    摘要翻译： 半导体器件包括布置在半导体衬底（1）的表面上的多个栅电极（6a，6b，6c，6d），绝缘层（5,8）覆盖了栅电极的顶部和侧壁。 在元件隔离区域（2）的表面上的相邻栅电极的相对侧壁之间的间隔小于栅电极侧壁的绝缘层中最薄绝缘层（8）的厚度的两倍 活性区的表面。 元件隔离区域上的栅电极之间的空间（14）填充有绝缘隔离层（8），使得要形成导电互连层（10）的元件隔离区域上的下面部分的不均匀性减小 防止导电互连层变薄，并且在图案化导电互连层时由于树脂膜的过度蚀刻而导致的断开。

    Method of manufacturing field effect transistor having a multilayer interconnection layer therein with tapered sidewall insulation
    5.
    发明授权
    Method of manufacturing field effect transistor having a multilayer interconnection layer therein with tapered sidewall insulation 失效
    具有其中具有锥形侧壁绝缘体的多层互连层的场效应晶体管的方法

    公开(公告)号：US5229314A

    公开(公告)日：1993-07-20

    申请号：US925153

    申请日：1992-08-06

    申请人： Tomonori Okudaira ,  Hideaki Arima ,  Makoto Ohi ,  Kaoru Motonami ,  Yasushi Matsui

    发明人： Tomonori Okudaira ,  Hideaki Arima ,  Makoto Ohi ,  Kaoru Motonami ,  Yasushi Matsui

    IPC分类号： H01L27/108 ,  H01L29/417 ,  H01L29/78

    CPC分类号： H01L29/41775 ,  H01L27/10817 ,  H01L29/7831

    摘要： A field effect transistor and a method of manufacturing thereof are disclosed that is not reduced in the characteristic of withstanding voltage between multilayer interconnection layers even when scaled to a higher integration. This field effect transistor includes side walls 21a formed on both sides of a bit line 15 so that the bottom side end contacts the upper surface of side walls 20a of gate electrodes 4b and 4c. The thickness of an insulating film interposed between gate electrodes 4b and 4c and a base portion 11a forming a low electrode 11 of a capacitor is not reduced. The characteristic of withstanding voltage is not deteriorated between multilayer interconnection layers even when scaled to higher integration.

    摘要翻译： 公开了一种场效应晶体管及其制造方法，即使在缩小到更高的集成度时，也不会降低多层互连层之间的耐电压特性。 该场效应晶体管包括形成在位线15两侧的侧壁21a，使得底侧端接触栅电极4b和4c的侧壁20a的上表面。 插入在栅电极4b和4c之间的绝缘膜的厚度和形成电容器的低电极11的基部11a的厚度不降低。 即使缩放到更高的集成度，耐压电压的特性也不会在多层互连层之间劣化。

    Field effect transistor having a multilayer interconnection layer therein with tapered sidewall insulators
    6.
    发明授权
    Field effect transistor having a multilayer interconnection layer therein with tapered sidewall insulators 失效
    具有锥形绝缘子的多层互连层的场效应晶体管

    公开(公告)号：US5157469A

    公开(公告)日：1992-10-20

    申请号：US685398

    申请日：1991-04-16

    申请人： Tomonori Okudaira ,  Hideaki Arima ,  Makoto Ohi ,  Kaoru Motonami ,  Yasushi Matsui

    发明人： Tomonori Okudaira ,  Hideaki Arima ,  Makoto Ohi ,  Kaoru Motonami ,  Yasushi Matsui

    IPC分类号： H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/417 ,  H01L29/78

    CPC分类号： H01L29/41775 ,  H01L27/10817 ,  H01L29/7831 ,  Y10S257/90

    摘要： A field effect transistor and a method of manufacturing thereof are disclosed that is not reduced in the characteristic of withstanding voltage between multilayer interconnection layers even when scaled to a higher integration. This field effect transistor includes side walls 21a formed on both sides of a bit line 15 so that the bottom side end contacts the upper surface of side walls 20a of gate electrodes 4b and 4c. The thickness of an insulating film interposed between gate electrodes 4b and 4c and a base portion 11a forming a low electrode 11 of a capacitor is not reduced. The characteristic of withstanding voltage is not deteriorated between multilayer interconnection layers even when scaled to higher integration.

    摘要翻译： 公开了一种场效应晶体管及其制造方法，即使在缩小到更高的集成度时，也不会降低多层互连层之间的耐电压特性。 该场效应晶体管包括形成在位线15两侧的侧壁21a，使得底侧端接触栅电极4b和4c的侧壁20a的上表面。 插入在栅电极4b和4c之间的绝缘膜的厚度和形成电容器的低电极11的基部11a的厚度不降低。 即使缩放到更高的集成度，耐压电压的特性也不会在多层互连层之间劣化。

    Strained multiple quantum well semiconductor laser and a method for producing the same
    8.
    发明授权
    Strained multiple quantum well semiconductor laser and a method for producing the same 失效
    应变多量子阱半导体激光器及其制造方法

    公开(公告)号：US5339325A

    公开(公告)日：1994-08-16

    申请号：US101933

    申请日：1993-08-04

    申请人： Masahiro Kito ,  Yasushi Matsui

    发明人： Masahiro Kito ,  Yasushi Matsui

    IPC分类号： H01S5/00 ,  H01S5/042 ,  H01S5/227 ,  H01S5/34 ,  H01S5/343 ,  H01S3/19

    CPC分类号： B82Y20/00 ,  H01S5/34 ,  H01S5/34313 ,  H01S5/2275 ,  H01S5/3403 ,  H01S5/3406 ,  H01S5/3407 ,  H01S5/34306 ,  Y10S438/938

    摘要： A strained multiple quantum well semiconductor laser including a semiconductor substrate, a multiple quantum well active layer including a plurality quantum well layers and a plurality of barrier layers, and a multilayer structure including the above multiple quantum well active layer is provided. Each barrier layer is interposed between two of the multiple quantum well active layers. The multilayer structure is formed upon the semiconductor substrate. Herein, at least one of the plurality of barrier layers is thicker than the other barrier layers, thereby serving as a layer absorbing strain which is stored in the barrier layers due to a difference between the lattice constant of semiconductor substrate and the lattice constant each quantum well layer.

    摘要翻译： 提供了包括半导体衬底的应变量子阱半导体激光器，包括多个量子阱层和多个势垒层的多量子阱活性层以及包括上述多量子阱活性层的多层结构。 每个阻挡层插入在多个量子阱活性层中的两个之间。 多层结构形成在半导体衬底上。 这里，多个阻挡层中的至少一个比其他阻挡层厚，从而由于半导体衬底的晶格常数和每个量子之间的晶格常数之间的差异而被用作存储在势垒层中的层吸收应变 井层。

    Active matrix substrate and its manufacturing method
    9.
    发明授权
    Active matrix substrate and its manufacturing method 有权
    有源矩阵基板及其制造方法

    公开(公告)号：US07923729B2

    公开(公告)日：2011-04-12

    申请号：US12470978

    申请日：2009-05-22

    申请人： Kyoko Sawamizu ,  Makoto Ohtani ,  Yasushi Matsui

    发明人： Kyoko Sawamizu ,  Makoto Ohtani ,  Yasushi Matsui

    IPC分类号： H01L29/04 ,  H01L29/10

    CPC分类号： G02F1/136213 ,  G02F1/136227 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/3244 ,  H01L51/56

    摘要： An active matrix substrate with a high aperture ratio is provided, which is capable of preventing electrical short circuits between pixel electrodes and auxiliary capacitive electrodes. Gate lines and auxiliary capacitive electrodes are formed on an insulated substrate. The auxiliary capacitive electrodes have holes formed therethrough. To cover the gate lines and the auxiliary capacitive electrodes, a first interlayer insulating film is formed, on which source lines, a semiconductor layer, and drain electrodes are formed. Then, a second interlayer insulating film is formed to cover all those layers. In the second interlayer insulating film, contact holes are formed to reach the drain electrodes in areas corresponding to the areas of the holes. Pixel electrodes formed on the second interlayer insulating film are connected to the drain electrodes through the contact holes.

    摘要翻译： 提供具有高开口率的有源矩阵基板，其能够防止像素电极和辅助电容电极之间的电短路。 栅极线和辅助电容电极形成在绝缘基板上。 辅助电容电极具有从其形成的孔。 为了覆盖栅极线和辅助电容电极，形成第一层间绝缘膜，在其上形成源极线，半导体层和漏极。 然后，形成第二层间绝缘膜以覆盖所有这些层。 在第二层间绝缘膜中，形成接触孔到达与孔的区域对应的区域中的漏电极。 形成在第二层间绝缘膜上的像素电极通过接触孔与漏电极连接。