公开(公告)号：US20050121804A1

公开(公告)日：2005-06-09

申请号：US10730834

申请日：2003-12-08

申请人： Nick Kuo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Chu-Fu Lin

发明人： Nick Kuo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Chu-Fu Lin

IPC分类号： H01L23/31 ,  H01L23/48 ,  H01L23/485

CPC分类号： H01L24/05 ,  H01L22/32 ,  H01L23/3171 ,  H01L24/10 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48647 ,  H01L2224/73207 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552

摘要： A chip structure comprising a semiconductor substrate, a plurality of dielectric layers, a plurality of circuit layers, a passivation layer, a metal layer and at least a bump. The semiconductor substrate has a plurality of electronic devices positioned on a surface layer of the semiconductor substrate. The dielectric layers are sequentially stacked on the semiconductor substrate and have a plurality of via holes. The circuit layers are disposed on one of the dielectric layers, wherein the circuit layers are electrically connected with each other through the via holes and are electrically connected to the electronic devices. The passivation layer is disposed over the circuit layers and the dielectric layers, wherein the passivation layer comprises an opening that exposes one of the metal layers. The metal layer is disposed over the passivation layer, wherein the metal layer comprises at least a bump pad and at least a testing pad, the bump pad electrically connecting with the testing pad. The bump is disposed on the bump pad.

摘要翻译： 一种芯片结构，包括半导体衬底，多个电介质层，多个电路层，钝化层，金属层和至少一个凸块。 半导体衬底具有位于半导体衬底的表面层上的多个电子器件。 电介质层依次层叠在半导体基板上，具有多个通路孔。 电路层设置在电介质层之一上，其中电路层通过通孔彼此电连接并电连接到电子器件。 钝化层设置在电路层和电介质层之上，其中钝化层包括暴露金属层之一的开口。 金属层设置在钝化层上，其中金属层至少包括凸块焊盘和至少一个测试焊盘，该焊盘与测试焊盘电连接。 凸块设置在凸块上。

公开(公告)号：US20080224326A1

公开(公告)日：2008-09-18

申请号：US12127794

申请日：2008-05-27

申请人： Nick Kuo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Chu-Fu Lin

发明人： Nick Kuo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Chu-Fu Lin

IPC分类号： H01L23/52

CPC分类号： H01L24/05 ,  H01L22/32 ,  H01L23/3171 ,  H01L24/10 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48647 ,  H01L2224/73207 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552

摘要： A chip structure comprising a semiconductor substrate, a plurality of dielectric layers, a plurality of circuit layers, a passivation layer, a metal layer and at least a bump. The semiconductor substrate has a plurality of electronic devices positioned on a surface layer of the semiconductor substrate. The dielectric layers are sequentially stacked on the semiconductor substrate and have a plurality of via holes. The circuit layers are disposed on one of the dielectric layers, wherein the circuit layers are electrically connected with each other through the via holes and are electrically connected to the electronic devices. The passivation layer is disposed over the circuit layers and the dielectric layers, wherein the passivation layer comprises an opening that exposes one of the metal layers. The metal layer is disposed over the passivation layer, wherein the metal layer comprises at least a bump pad and at least a testing pad, the bump pad electrically connecting with the testing pad. The bump is disposed on the bump pad.

摘要翻译： 一种芯片结构，包括半导体衬底，多个电介质层，多个电路层，钝化层，金属层和至少一个凸块。 半导体衬底具有位于半导体衬底的表面层上的多个电子器件。 电介质层依次层叠在半导体基板上，具有多个通路孔。 电路层设置在电介质层之一上，其中电路层通过通孔彼此电连接并电连接到电子器件。 钝化层设置在电路层和电介质层之上，其中钝化层包括暴露金属层之一的开口。 金属层设置在钝化层上，其中金属层至少包括凸块焊盘和至少一个测试焊盘，该焊盘与测试焊盘电连接。 凸块设置在凸块上。

公开(公告)号：US20110049515A1

公开(公告)日：2011-03-03

申请号：US12941069

申请日：2010-11-07

申请人： Nick Kuo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Chu-Fu Lin

发明人： Nick Kuo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Chu-Fu Lin

IPC分类号： H01L23/492 ,  H01L23/482

CPC分类号： H01L24/05 ,  H01L22/32 ,  H01L23/3171 ,  H01L24/10 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48647 ,  H01L2224/73207 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552

摘要： A chip structure comprising a silicon substrate, a MOS device, dielectric layers, a metallization structure, a passivation layer, a plurality of metal layers and a polymer layer. The metallization structure comprises a first circuit layer and a second circuit layer over the first circuit layer, and comprises a damascene electroplated copper. The passivation layer is over the metallization structure and dielectric layers, the passivation layer including a first opening exposing a contact point of the metallization structure. The polymer layer is disposed over the passivation layer and the first metal layer, a second opening in the polymer layer being over a second contact point of the first metal layer, the polymer layer covering a top surface and sidewall of the first metal layer. The second contact point is connected to the first contact point through the first opening, the second opening not being vertically over the first opening.

摘要翻译： 一种芯片结构，包括硅衬底，MOS器件，电介质层，金属化结构，钝化层，多个金属层和聚合物层。 金属化结构包括在第一电路层上的第一电路层和第二电路层，并且包括镶嵌电镀铜。 钝化层在金属化结构和电介质层之上，钝化层包括暴露金属化结构的接触点的第一开口。 聚合物层设置在钝化层和第一金属层之上，聚合物层中的第二开口在第一金属层的第二接触点之上，聚合物层覆盖第一金属层的顶表面和侧壁。 第二接触点通过第一开口连接到第一接触点，第二开口不垂直于第一开口。

公开(公告)号：US07855461B2

公开(公告)日：2010-12-21

申请号：US12127794

申请日：2008-05-27

申请人： Nick Kuo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Chu-Fu Lin

发明人： Nick Kuo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Chu-Fu Lin

IPC分类号： H01L23/43

CPC分类号： H01L24/05 ,  H01L22/32 ,  H01L23/3171 ,  H01L24/10 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48647 ,  H01L2224/73207 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552

摘要： A chip structure comprising a semiconductor substrate, a plurality of dielectric layers, a plurality of circuit layers, a passivation layer, a metal layer and at least a bump. The semiconductor substrate has a plurality of electronic devices positioned on a surface layer of the semiconductor substrate. The dielectric layers are sequentially stacked on the semiconductor substrate and have a plurality of via holes. The circuit layers are disposed on one of the dielectric layers, wherein the circuit layers are electrically connected with each other through the via holes and are electrically connected to the electronic devices. The passivation layer is disposed over the circuit layers and the dielectric layers, wherein the passivation layer comprises an opening that exposes one of the metal layers. The metal layer is disposed over the passivation layer, wherein the metal layer comprises at least a bump pad and at least a testing pad, the bump pad electrically connecting with the testing pad. The bump is disposed on the bump pad.

摘要翻译： 一种芯片结构，包括半导体衬底，多个电介质层，多个电路层，钝化层，金属层和至少一个凸块。 半导体衬底具有位于半导体衬底的表面层上的多个电子器件。 电介质层依次层叠在半导体基板上，具有多个通路孔。 电路层设置在电介质层之一上，其中电路层通过通孔彼此电连接并电连接到电子器件。 钝化层设置在电路层和电介质层之上，其中钝化层包括暴露金属层之一的开口。 金属层设置在钝化层上，其中金属层至少包括凸块焊盘和至少一个测试焊盘，该焊盘与测试焊盘电连接。 凸块设置在凸块上。

公开(公告)号：US07977803B2

公开(公告)日：2011-07-12

申请号：US12941069

申请日：2010-11-07

申请人： Nick Kuo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Chu-Fu Lin

发明人： Nick Kuo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Chu-Fu Lin

IPC分类号： H01L23/43

CPC分类号： H01L24/05 ,  H01L22/32 ,  H01L23/3171 ,  H01L24/10 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48647 ,  H01L2224/73207 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552

摘要： A chip structure comprising a silicon substrate, a MOS device, dielectric layers, a metallization structure, a passivation layer, a plurality of metal layers and a polymer layer. The metallization structure comprises a first circuit layer and a second circuit layer over the first circuit layer, and comprises a damascene electroplated copper. The passivation layer is over the metallization structure and dielectric layers, the passivation layer including a first opening exposing a contact point of the metallization structure. The polymer layer is disposed over the passivation layer and the first metal layer, a second opening in the polymer layer being over a second contact point of the first metal layer, the polymer layer covering a top surface and sidewall of the first metal layer. The second contact point is connected to the first contact point through the first opening, the second opening not being vertically over the first opening.

摘要翻译： 一种芯片结构，包括硅衬底，MOS器件，电介质层，金属化结构，钝化层，多个金属层和聚合物层。 金属化结构包括在第一电路层上的第一电路层和第二电路层，并且包括镶嵌电镀铜。 钝化层在金属化结构和电介质层之上，钝化层包括暴露金属化结构的接触点的第一开口。 聚合物层设置在钝化层和第一金属层之上，聚合物层中的第二开口在第一金属层的第二接触点之上，聚合物层覆盖第一金属层的顶表面和侧壁。 第二接触点通过第一开口连接到第一接触点，第二开口不垂直于第一开口。

公开(公告)号：US07394161B2

公开(公告)日：2008-07-01

申请号：US10730834

申请日：2003-12-08

申请人： Nick Kuo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Chu-Fu Lin

发明人： Nick Kuo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Chu-Fu Lin

IPC分类号： H01L23/43

CPC分类号： H01L24/05 ,  H01L22/32 ,  H01L23/3171 ,  H01L24/10 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48647 ,  H01L2224/73207 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552

摘要： A chip structure comprising a semiconductor substrate, a plurality of dielectric layers, a plurality of circuit layers, a passivation layer, a metal layer and at least a bump. The semiconductor substrate has a plurality of electronic devices positioned on a surface layer of the semiconductor substrate. The dielectric layers are sequentially stacked on the semiconductor substrate and have a plurality of via holes. The circuit layers are disposed on one of the dielectric layers, wherein the circuit layers are electrically connected with each other through the via holes and are electrically connected to the electronic devices. The passivation layer is disposed over the circuit layers and the dielectric layers, wherein the passivation layer comprises an opening that exposes one of the metal layers. The metal layer is disposed over the passivation layer, wherein the metal layer comprises at least a bump pad and at least a testing pad, the bump pad electrically connecting with the testing pad. The bump is disposed on the bump pad.

摘要翻译： 一种芯片结构，包括半导体衬底，多个电介质层，多个电路层，钝化层，金属层和至少一个凸块。 半导体衬底具有位于半导体衬底的表面层上的多个电子器件。 电介质层依次层叠在半导体基板上，具有多个通路孔。 电路层设置在电介质层之一上，其中电路层通过通孔彼此电连接并电连接到电子器件。 钝化层设置在电路层和电介质层之上，其中钝化层包括暴露金属层之一的开口。 金属层设置在钝化层上，其中金属层至少包括凸块焊盘和至少一个测试焊盘，该焊盘与测试焊盘电连接。 凸块设置在凸块上。