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公开(公告)号：US20110148890A1
公开(公告)日：2011-06-23
申请号：US12655124
申请日：2009-12-23
申请人： Nikos Kaburlasos , Inder M. Sodhi
发明人： Nikos Kaburlasos , Inder M. Sodhi
CPC分类号： G06F1/329 , G06F1/3228 , G06T1/20 , Y02D10/24 , Y02D50/20
摘要： An electronic device comprises a central processing unit, a graphics processing un and a power control unit comprising logic to develop a predictive model of power states for a central processing unit in the electronic device, and use the predictive model to synchronize activity of a graphics processing unit in the electronic device with periods of activity in the central processing unit. Other embodiments may be described.
摘要翻译： 电子设备包括中央处理单元，图形处理单元和功率控制单元，其包括用于开发电子设备中的中央处理单元的功率状态的预测模型的逻辑，并且使用预测模型来同步图形处理的活动 在中央处理单元中具有活动周期的电子设备中的单元。 可以描述其他实施例。
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公开(公告)号：US08279213B2
公开(公告)日：2012-10-02
申请号：US12655124
申请日：2009-12-23
申请人： Nikos Kaburlasos , Inder M. Sodhi
发明人： Nikos Kaburlasos , Inder M. Sodhi
CPC分类号： G06F1/329 , G06F1/3228 , G06T1/20 , Y02D10/24 , Y02D50/20
摘要： An electronic device comprises a central processing unit, a graphics processing unit, and a power control unit comprising logic to develop a predictive model of power states for a central processing unit in the electronic device, and use the predictive model to synchronize activity of a graphics processing unit in the electronic device with periods of activity in the central processing unit. Other embodiments may be described.
摘要翻译： 电子设备包括中央处理单元，图形处理单元和功率控制单元，其包括用于开发电子设备中的中央处理单元的功率状态的预测模型的逻辑，并且使用预测模型来同步图形的活动 处理单元，其具有在中央处理单元中的活动周期的电子设备。 可以描述其他实施例。
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公开(公告)号：US10025367B2
公开(公告)日：2018-07-17
申请号：US14463573
申请日：2014-08-19
申请人： Nikos Kaburlasos , Eric Samson
发明人： Nikos Kaburlasos , Eric Samson
IPC分类号： G06F1/32
摘要： In one embodiment execution units, graphics cores, or graphics sub-cores can be dynamically scaled across a frame of graphics operations. Available execution units within each graphics core may be scaled using utilization metrics such as the current utilization rate of the execution units and the submission of new draw calls. In one embodiment, one of more of the sub-cores within each graphics core may be enable or disabled based on current or past utilization of the sub-cores based on a set of current graphics operations.
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公开(公告)号：US08209480B2
公开(公告)日：2012-06-26
申请号：US12835525
申请日：2010-07-13
申请人： Nikos Kaburlasos , Jim Kardaeh
发明人： Nikos Kaburlasos , Jim Kardaeh
IPC分类号： G06F12/02
CPC分类号： G06F12/0292 , G11C11/406 , G11C11/40615 , G11C2211/4067 , Y02D10/13
摘要： In some embodiments, an electronic apparatus comprises a communication interface, an input/output interface, a processor, and logic to collect, in the electronic apparatus, a first identifier associated with a first communication device and second identifier associated with a second communication device, logic to establish a communication connection between the electronic apparatus and the first communication device, and logic to initiate, in the electronic apparatus, a connection request for a communication connection between the first communication device and the second communication device. Other embodiments may be described.
摘要翻译： 在一些实施例中，电子设备包括通信接口，输入/输出接口，处理器和在电子设备中收集与第一通信设备相关联的第一标识符和与第二通信设备相关联的第二标识符的逻辑， 在电子设备和第一通信设备之间建立通信连接的逻辑，以及在电子设备中启动第一通信设备和第二通信设备之间的通信连接的连接请求的逻辑。 可以描述其他实施例。
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公开(公告)号：US08095725B2
公开(公告)日：2012-01-10
申请号：US11967296
申请日：2007-12-31
申请人： Jim Kardach , Nikos Kaburlasos
发明人： Jim Kardach , Nikos Kaburlasos
IPC分类号： G06F12/02
CPC分类号： G11C11/40618 , G06F12/0223 , G06F12/06 , G06F12/0607 , G06F2212/1028 , G11C7/1072 , G11C11/406 , G11C11/40622 , Y02D10/13
摘要： Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random Access Memory (DRAM) units to store data, wherein each DRAM unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said DIMM to a memory page of an Operating System, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the Operating System.
摘要翻译： 设备，系统和内存分配方法。 例如，一种装置包括：包括存储数据的多个动态随机存取存储器（DRAM）单元的双列直插存储器模块（DIMM），其中每个DRAM单元包括多个存储体，并且每个存储体被分成多个 的子银行; 以及存储器管理单元，用于将所述DIMM的交织子组的一组分配给操作系统的存储器页，其中所述交织子组的组合存储器大小等于所述存储器页的大小 操作系统。
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公开(公告)号：US07757039B2
公开(公告)日：2010-07-13
申请号：US11901502
申请日：2007-09-18
申请人： Nikos Kaburlasos , Jim Kardach
发明人： Nikos Kaburlasos , Jim Kardach
CPC分类号： G06F12/0292 , G11C11/406 , G11C11/40615 , G11C2211/4067 , Y02D10/13
摘要： In some embodiments, an electronic apparatus comprises a communication interface, an input/output interface, a processor, and logic to collect, in the electronic apparatus, a first identifier associated with a first communication device and second identifier associated with a second communication device, logic to establish a communication connection between the electronic apparatus and the first communication device, and logic to initiate, in the electronic apparatus, a connection request for a communication connection between the first communication device and the second communication device. Other embodiments may be described.
摘要翻译： 在一些实施例中，电子设备包括通信接口，输入/输出接口，处理器和在电子设备中收集与第一通信设备相关联的第一标识符和与第二通信设备相关联的第二标识符的逻辑， 在电子设备和第一通信设备之间建立通信连接的逻辑，以及在电子设备中启动第一通信设备和第二通信设备之间的通信连接的连接请求的逻辑。 可以描述其他实施例。
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公开(公告)号：US07478214B2
公开(公告)日：2009-01-13
申请号：US11325887
申请日：2006-01-04
申请人： Nikos Kaburlasos
发明人： Nikos Kaburlasos
CPC分类号： G06F13/4243 , Y02D10/14 , Y02D10/151
摘要： A method and apparatus for gating a clock signal to one or more embedded blocks of a random access memory (RAM), is described. In one embodiment, a clock gating block is coupled to a RAM EBB, the clock-gating block to provide a RAM clock when receiving read and write enable signals and to provide a gated clock signal when the RAM EBB is idle. In another embodiment, a clock gating block is coupled to a RAM bank, having a plurality of RAM EBBs, the clock-gating block to provide a RAM clock to the RAM bank when receiving read and write enable signals and to provide a gated clock signal to the RAM bank when the RAM bank is idle.
摘要翻译： 描述了用于将时钟信号选通到随机存取存储器（RAM）的一个或多个嵌入块的方法和装置。 在一个实施例中，时钟门控模块耦合到RAM EBB，时钟门控模块，当接收到读和写使能信号时提供RAM时钟，并在RAM EBB空闲时提供选通时钟信号。 在另一个实施例中，时钟门控模块耦合到具有多个RAM EBB的RAM存储体，时钟门控模块在接收到读和写使能信号时向RAM存储体提供RAM时钟，并提供门控时钟信号 到RAM存储区时，RAM存储空闲。
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8.发明申请公开(公告)号：US20190261122A1
公开(公告)日：2019-08-22
申请号：US16269778
申请日：2019-02-07
申请人： Joydeep Ray , Travis T. Schluessler , Prasoonkumar Surti , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Abhishek R. Appu , James M. Holland , Jeffery S. Boles , Jonathan Kennedy , Louis Feng , Atsuo Kuwahara , Barnan Das , Narayan Biswal , Stanley J. Baran , Gokcen Cilingir , Nilesh V. Shah , Archie Sharma , Mayuresh M. Varerkar
发明人： Joydeep Ray , Travis T. Schluessler , Prasoonkumar Surti , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Abhishek R. Appu , James M. Holland , Jeffery S. Boles , Jonathan Kennedy , Louis Feng , Atsuo Kuwahara , Barnan Das , Narayan Biswal , Stanley J. Baran , Gokcen Cilingir , Nilesh V. Shah , Archie Sharma , Mayuresh M. Varerkar
摘要： Systems, apparatuses and methods may provide away to render augmented reality (AR) and/or virtual reality (VR) sensory enhancements using ray tracing. More particularly, systems, apparatuses and methods may provide a way to normalize environment information captured by multiple capture devices, and calculate, for an observer, the sound sources or sensed events vector paths. The systems, apparatuses and methods may detect and/or manage one or more capture devices and assign one or more the capture devices based on one or more conditions to provide observer an immersive VR/AR experience.
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公开(公告)号：US10242418B2
公开(公告)日：2019-03-26
申请号：US13993696
申请日：2011-11-21
申请人： Nikos Kaburlasos , Eric C. Samson
发明人： Nikos Kaburlasos , Eric C. Samson
IPC分类号： G06T1/20 , G09G5/36 , G06F1/32 , G06F1/26 , G06F1/3203 , G06F1/324 , G06F1/3234 , G06F1/3287
摘要： Power gating a portion of a graphics processor may be used to improve performance or to achieve a power budget. A processor granularity, such as a slice or subslice, may be gated.
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公开(公告)号：US09942593B2
公开(公告)日：2018-04-10
申请号：US13024536
申请日：2011-02-10
IPC分类号： G10L19/022 , G10L21/055 , H04N21/4143 , H04N21/426 , H04N19/44 , H04N19/42
CPC分类号： H04N21/4143 , H04N19/42 , H04N19/44 , H04N21/42607 , H04N21/42653
摘要： Techniques are disclosed that involve the processing of audio streams. For instance, a host processing platform may receive a content stream that includes an encoded audio stream. In turn, a graphics engine produces from it a decoded audio stream. This producing may involve the graphics engine performing various operations, such as an entropy decoding operation, an inverse quantization operation, and an inverse discrete cosine transform operation. In embodiments, the content stream may further include an encoded video stream. Thus the graphics engine may produce from it a decoded video stream. This audio and video decoding may be performed in parallel.
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