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8 条记录 (耗时 0.016 秒)

    Transimpedance Amplifier
    2.
    发明申请
    Transimpedance Amplifier 有权

    公开(公告)号：US20220224298A1

    公开(公告)日：2022-07-14

    申请号：US17607298

    申请日：2019-05-08

    申请人： Nippon Telegraph and Telephone Corporation

    发明人： Hiroaki Katsurai ,  Kimikazu Sano

    IPC分类号： H03F3/45

    摘要： A reset signal is generated by a TIA circuit alone. In an embodiment, a transimpedance amplifier configured to convert a current signal into a voltage signal includes a transimpedance stage including an amplification stage constituted of a transistor with a grounded emitter, and a comparator configured to compare a collector voltage of the transistor with a reference voltage and output a reset signal.

    Track-and-hold circuit
    3.
    发明授权
    Track-and-hold circuit 有权

    公开(公告)号：US11056209B2

    公开(公告)日：2021-07-06

    申请号：US16978356

    申请日：2019-03-04

    申请人： Nippon Telegraph and Telephone Corporation

    发明人： Hiroaki Katsurai ,  Naoki Miura ,  Hiroyuki Fukuyama ,  Hideyuki Nosaka

    IPC分类号： G11C27/02 ,  H03K5/13 ,  H03M1/12

    摘要： A track-and-hold circuit with a high sampling rate and reduced power consumption is provided. A track-and-hold circuit performing switching between a track mode in which a data signal that is equivalent to an input data signal is output and a hold mode in which a data signal which is input at a time of switching from the track mode to the hold mode is held and output, by using a clock signal, such that only the data signal in the hold mode is output, the track-and-hold circuit including: two sampling circuits configured to be connected in parallel to an input of the data signal and receive an in-phase data signal; a clock circuit configured to input a clock signal, which has a phase opposite to a phase of a clock signal input to one of the two sampling circuits, to the other of the two sampling circuits; and a multiplexer circuit configured to select and output a data output of either one of the two sampling circuits that is in the hold mode, by using the clock signal.

    Transimpedance Amplifier
    5.
    发明申请
    Transimpedance Amplifier 有权

    公开(公告)号：US20220216841A1

    公开(公告)日：2022-07-07

    申请号：US17604672

    申请日：2019-05-08

    申请人： Nippon Telegraph and Telephone Corporation

    发明人： Hiroaki Katsurai ,  Kimikazu Sano

    IPC分类号： H03F3/45 ,  H03K19/21 ,  H03G3/30 ,  H03F1/02

    摘要： A reset signal is generated by a TIA circuit alone. In an embodiment, a transimpedance amplifier configured to convert a current signal into a voltage signal includes a transimpedance stage, a gain control circuit configured to compare an output of the transimpedance stage with a reference voltage and output a gain control voltage, and a reset signal output circuit configured to output a reset signal having a predetermined pulse width at a timing of at least one of a rise or a fall of the gain control voltage.

    Track-and-Hold Circuit
    6.
    发明申请
    Track-and-Hold Circuit 有权

    公开(公告)号：US20210012848A1

    公开(公告)日：2021-01-14

    申请号：US16978356

    申请日：2019-03-04

    申请人： Nippon Telegraph and Telephone Corporation

    发明人： Hiroaki Katsurai ,  Naoki Miura ,  Hiroyuki Fukuyama ,  Hideyuki Nosaka

    IPC分类号： G11C27/02

    摘要： A track-and-hold circuit with a high sampling rate and reduced power consumption is provided. A track-and-hold circuit performing switching between a track mode in which a data signal that is equivalent to an input data signal is output and a hold mode in which a data signal which is input at a time of switching from the track mode to the hold mode is held and output, by using a clock signal, such that only the data signal in the hold mode is output, the track-and-hold circuit including: two sampling circuits configured to be connected in parallel to an input of the data signal and receive an in-phase data signal; a clock circuit configured to input a clock signal, which has a phase opposite to a phase of a clock signal input to one of the two sampling circuits, to the other of the two sampling circuits; and a multiplexer circuit configured to select and output a data output of either one of the two sampling circuits that is in the hold mode, by using the clock signal.