公开(公告)号：US20060232288A1

公开(公告)日：2006-10-19

申请号：US11398694

申请日：2006-04-06

申请人： Noboru Okane ,  Ryoji Matsushima ,  Kazuhiro Yamamori ,  Junya Sagara ,  Yoshio Iizuka ,  Kuniyuki Ohnishi

发明人： Noboru Okane ,  Ryoji Matsushima ,  Kazuhiro Yamamori ,  Junya Sagara ,  Yoshio Iizuka ,  Kuniyuki Ohnishi

IPC分类号： G01R31/02

CPC分类号： H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L24/92 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/48475 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor device has a plurality of bare chips stacked on at least one of first and second main surfaces oppositely arranged on a support substrate, spacers arranged between two bare chips arranged adjacently in up and down direction among the plurality of bare chips, and inner leads which are arranged at both sides in a horizontal direction of the support substrate and are connected to pads of the bare chips via bonding wires, wherein the bonding wires which connect the pads of the bare chips at one end side of the spacers to the corresponding inner leads, are arranged not to contact the bare chip at the other end side of the same spacer.

公开(公告)号：US07569921B2

公开(公告)日：2009-08-04

申请号：US11398694

申请日：2006-04-06

申请人： Noboru Okane ,  Ryoji Matsushima ,  Kazuhiro Yamamori ,  Junya Sagara ,  Yoshio Iizuka ,  Kuniyuki Ohnishi

发明人： Noboru Okane ,  Ryoji Matsushima ,  Kazuhiro Yamamori ,  Junya Sagara ,  Yoshio Iizuka ,  Kuniyuki Ohnishi

IPC分类号： H01L23/02

CPC分类号： H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L24/92 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/48475 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor device has a plurality of bare chips stacked on at least one of first and second main surfaces oppositely arranged on a support substrate, spacers arranged between two bare chips arranged adjacently in up and down direction among the plurality of bare chips, and inner leads which are arranged at both sides in a horizontal direction of the support substrate and are connected to pads of the bare chips via bonding wires, wherein the bonding wires which connect the pads of the bare chips at one end side of the spacers to the corresponding inner leads, are arranged not to contact the bare chip at the other end side of the same spacer.

摘要翻译： 半导体器件具有堆叠在与支撑基板相对布置的第一和第二主表面中的至少一个上的多个裸芯片，布置在多个裸芯片之间沿上下方向布置的两个裸芯片之间的间隔物和内引线 其布置在支撑基板的水平方向的两侧，并且通过接合线连接到裸芯片的焊盘，其中，将间隔件的一端侧的裸芯片的焊盘连接到相应的内部的接合线 引线被布置成不与相同间隔物的另一端侧的裸芯片接触。

公开(公告)号：US20070023922A1

公开(公告)日：2007-02-01

申请号：US11490022

申请日：2006-07-21

申请人： Noboru Okane ,  Ryoji Matsushima ,  Kazuhiro Yamamori ,  Junya Sagara ,  Yoshio Iizuka ,  Kuniyuki Oonishi

发明人： Noboru Okane ,  Ryoji Matsushima ,  Kazuhiro Yamamori ,  Junya Sagara ,  Yoshio Iizuka ,  Kuniyuki Oonishi

IPC分类号： H01L23/48

CPC分类号： H01L25/0657 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package includes a circuit board having connection pads formed on a front and back surfaces, and a wiring network connected to these connection pads, as a package base. Metal bumps connected to at least part of the connection pads on the front and back surfaces via the wiring network are formed on the back surface of the circuit board as external connection terminals. One or a plurality of semiconductor elements electrically connected to the connection pad on the front surface side is or are mounted on a first element mounting part provided on the front surface side of the circuit board. One or plurality of semiconductor elements electrically connected to the connection pad on the back surface side is or are mounted on a second element mounting part provided on the back surface side of the circuit board.

摘要翻译： 半导体封装包括具有形成在前表面和后表面上的连接焊盘的电路板和连接到这些连接焊盘的布线网络作为封装基座。 通过布线网络连接到前表面和后表面上的连接焊盘的至少一部分的金属凸块形成在电路板的背面上作为外部连接端子。 电连接到前表面侧的连接焊盘的一个或多个半导体元件被安装在设置在电路板的前表面侧的第一元件安装部分上。 电连接到背面侧的连接焊盘的一个或多个半导体元件被安装在设置在电路板的背面侧的第二元件安装部上。

公开(公告)号：US20070023875A1

公开(公告)日：2007-02-01

申请号：US11490116

申请日：2006-07-21

申请人： Noboru Okane ,  Ryoji Matsushima ,  Kazuhiro Yamamori ,  Junya Sagara ,  Yoshio Iizuka ,  Kuniyuki Oonishi ,  Atsushi Yoshimura

发明人： Noboru Okane ,  Ryoji Matsushima ,  Kazuhiro Yamamori ,  Junya Sagara ,  Yoshio Iizuka ,  Kuniyuki Oonishi ,  Atsushi Yoshimura

IPC分类号： H01L23/495

CPC分类号： H01L23/49575 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package includes a lead frame having an element mounting part and a lead part. A first semiconductor element and a second semiconductor element are sequentially stacked on a principal surface at least on one side of the element mounting part. An insulating resin layer serving as a second adhesive layer is filled between the first semiconductor element and the second semiconductor element. An element-side end portion of a first bonding wire connected to the first semiconductor element is buried in the insulating resin layer.

摘要翻译： 半导体封装包括具有元件安装部分和引线部分的引线框架。 第一半导体元件和第二半导体元件依次堆叠在元件安装部的至少一侧的主表面上。 用作第二粘合剂层的绝缘树脂层填充在第一半导体元件和第二半导体元件之间。 连接到第一半导体元件的第一接合线的元件侧端部埋设在绝缘树脂层中。

公开(公告)号：US5292050A

公开(公告)日：1994-03-08

申请号：US985111

申请日：1992-12-03

申请人： Tetsuya Nagaoka ,  Kazuhiro Yamamori

发明人： Tetsuya Nagaoka ,  Kazuhiro Yamamori

IPC分类号： H01L21/00 ,  H01L21/60 ,  H01L21/603

CPC分类号： H01L24/85 ,  H01L24/48 ,  H01L24/78 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/78301 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01082

摘要： A wire bonder comprises a pattern recognition mechanism. The pattern recognition mechanism includes a TV camera head, a camera control unit, a program research unit, and a bonder controller. The bonder controller includes a microcomputer, a control circuit, and a servo drive unit. The TV camera head and camera control unit detect locations of a first bonding pad formed on a first semiconductor chip and a second bonding pad formed on a second semiconductor chip. The program research unit calculates amounts of shift of the detected locations of the first and second bonding pads from reference locations thereof. The microcomputer corrects locations of first and second bonding points and those of first and second cutting points in accordance with the calculated amounts of shift. The control circuit and servo drive unit control the first and second bonding points and the first and second cutting points based on the corrected locations.

摘要翻译： 引线接合器包括图案识别机构。 图案识别机构包括电视摄像机头，照相机控制单元，程序研究单元和接合器控制器。 接合器控制器包括微型计算机，控制电路和伺服驱动单元。 电视摄像机头和照相机控制单元检测形成在第一半导体芯片上的第一焊盘的位置和形成在第二半导体芯片上的第二焊盘。 程序研究单元从其参考位置计算第一和第二接合焊盘的检测位置的偏移量。 微型计算机根据计算出的移位量校正第一和第二接合点的位置以及第一和第二切割点的位置。 控制电路和伺服驱动单元基于校正的位置来控制第一和第二接合点以及第一和第二切割点。

公开(公告)号：US08039970B2

公开(公告)日：2011-10-18

申请号：US12021780

申请日：2008-01-29

申请人： Kazuhiro Yamamori ,  Katsuhiro Ishida

发明人： Kazuhiro Yamamori ,  Katsuhiro Ishida

IPC分类号： H01L23/49

CPC分类号： H01L24/85 ,  H01L23/3128 ,  H01L23/4952 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/78 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48475 ,  H01L2224/48479 ,  H01L2224/48599 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/8385 ,  H01L2224/85051 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/85986 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/20752 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/4554 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A stacked semiconductor device includes a first semiconductor element mounted on a circuit substrate and a second semiconductor element stacked on the first semiconductor element via a spacer layer. An electrode pad of the first semiconductor element is electrically connected to a connection portion of the circuit substrate through a first metal wire. A vicinity of the end portion of the first metal wire connected to the electrode pad is in contact with an insulating protection film which covers the surface of the first semiconductor element.

摘要翻译： 层叠半导体器件包括安装在电路基板上的第一半导体元件和经由间隔层堆叠在第一半导体元件上的第二半导体元件。 第一半导体元件的电极焊盘通过第一金属线电连接到电路基板的连接部分。 连接到电极焊盘的第一金属线的端部附近与覆盖第一半导体元件的表面的绝缘保护膜接触。