公开(公告)号：US06426640B1

公开(公告)日：2002-07-30

申请号：US09440803

申请日：1999-11-15

申请人： Norbert Wirth ,  Eric Cordes ,  Zoltan Manyoki ,  Dominique Savignac

发明人： Norbert Wirth ,  Eric Cordes ,  Zoltan Manyoki ,  Dominique Savignac

IPC分类号： G01R3102

CPC分类号： G01R31/2856 ,  G01R31/2884

摘要： The invention relates to a semiconductor module for a burn-in test configuration. The semiconductor module has a regulator which, when it is turned on, always supplies a constant low voltage to an internal circuit of the semiconductor module. The semiconductor module also contains a component which, when the burn-in voltage has been applied for a defined time period, supplies a different characteristic than when the internal voltage is applied.

摘要翻译： 本发明涉及一种用于老化测试配置的半导体模块。 半导体模块具有调节器，当其导通时，总是向半导体模块的内部电路提供恒定的低电压。 半导体模块还包含当在已经施加了预定时间段的老化电压时提供与施加内部电压不同的特性的组件。

公开(公告)号：US06693447B1

公开(公告)日：2004-02-17

申请号：US09277281

申请日：1999-03-26

申请人： Dominique Savignac ,  Frank Weber ,  Norbert Wirth

发明人： Dominique Savignac ,  Frank Weber ,  Norbert Wirth

IPC分类号： G01R3126

CPC分类号： G01R31/2884

摘要： A configuration for identifying contact faults during the testing of integrated circuits with a multiplicity of pins which protrude from a housing and are connected to respective pads on a semiconductor body of the integrated circuit. Pull-up or pull-down devices are connected between respective pads and input buffers and in each case hold the pads at a high or low potential by impressing a holding current, if contact has not been made with a pin associated with the pad during testing, the result being that activation of the circuit section connected to the pin is avoided.

摘要翻译： 用于在具有从壳体突出并且连接到集成电路的半导体主体上的相应焊盘的多个引脚的集成电路测试期间识别接触故障的配置。 上拉或下拉器件连接在相应的焊盘和输入缓冲器之间，并且在每种情况下，通过施加保持电流来将焊盘保持在高或低电位，如果在测试期间没有与焊盘相关联的引脚进行接触 结果是避免了与引脚连接的电路部分的激活。

公开(公告)号：US5905687A

公开(公告)日：1999-05-18

申请号：US904500

申请日：1997-08-01

申请人： Rudiger Brede ,  Dominique Savignac ,  Norbert Wirth

发明人： Rudiger Brede ,  Dominique Savignac ,  Norbert Wirth

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/789

摘要： The fuse refresh circuit for semiconductor memories has a set circuit for setting a fuse latch circuit. The fuse latch circuit is set by the set circuit in at least one refresh cycle after a voltage supply has been switched on. During the refresh cycle of the fuse latch circuit, the latter is driven with pulses in such a way that the state of the fuse latch circuit is evaluated and only an incorrectly set fuse latch circuit is set to be correct.

摘要翻译： 半导体存储器的保险丝刷新电路具有用于设定熔丝锁存电路的设定电路。 熔断器锁存电路在电源接通之后至少在一个刷新周期内由设定电路设置。 在保险丝锁存电路的刷新周期期间，后者用脉冲驱动，使得对熔丝锁存电路的状态进行评估，并且仅将不正确设置的熔丝锁存电路设置为正确。

公开(公告)号：US07260671B2

公开(公告)日：2007-08-21

申请号：US10278232

申请日：2002-10-23

申请人： Eric Cordes ,  Christian Stocken ,  Nazif Taskin ,  Norbert Wirth

发明人： Eric Cordes ,  Christian Stocken ,  Nazif Taskin ,  Norbert Wirth

IPC分类号： G06K19/10

CPC分类号： G11C7/1045 ,  G11C5/04 ,  G11C7/20 ,  G11C16/20

摘要： A memory module includes at least one memory chip arranged on the memory module. Information about the memory module and/or the at least one memory chip arranged on the memory module can be stored directly on the memory chip, making use of a suited element, fuses or flip-flops, for example. A memory chip contains such an element for containing information relating to the memory chip and/or a memory module with which the memory chip is compatible, wherein the information containing element can be read out by means of an external processor.

摘要翻译： 存储器模块包括布置在存储器模块上的至少一个存储器芯片。 关于存储器模块和/或布置在存储器模块上的至少一个存储器芯片的信息可以直接存储在存储器芯片上，例如使用适合的元件，保险丝或触发器。 存储器芯片包含用于存储与存储器芯片相关的信息的存储器芯片和/或与存储器芯片兼容的存储器模块的元件，其中信息包含元件可以通过外部处理器读出。

公开(公告)号：US20050133785A1

公开(公告)日：2005-06-23

申请号：US10995529

申请日：2004-11-24

申请人： Georg Eggers ,  Norbert Wirth ,  Herbert Benzinger ,  Thomas Huber

发明人： Georg Eggers ,  Norbert Wirth ,  Herbert Benzinger ,  Thomas Huber

IPC分类号： G01K7/01 ,  G01K7/22 ,  H01L23/58 ,  G01R31/26

CPC分类号： G01K7/01 ,  G01K7/226

摘要： The invention relates to a method and a device (1, 11, 21) for detecting the overheating of a semiconductor device, comprising a temperature measuring means (3, 13, 23) that changes its electrical conductivity when the temperature of the semiconductor device changes.

摘要翻译： 本发明涉及一种用于检测半导体器件过热的方法和装置（1,11,21），包括当半导体器件的温度变化时改变其导电性的温度测量装置（3,13,23） 。

公开(公告)号：US06618303B2

公开(公告)日：2003-09-09

申请号：US09929303

申请日：2001-08-13

申请人： Arndt Gruber ,  Ralf Schneider ,  Bernhard Ruf ,  Norbert Wirth

发明人： Arndt Gruber ,  Ralf Schneider ,  Bernhard Ruf ,  Norbert Wirth

IPC分类号： G11C700

CPC分类号： G11C29/006 ,  G11C2029/2602

摘要： An electronic circuit in an integrated circuit having memory cells is described. The circuit permits information to be written to particular memory cells only once, so that subsequent writing to the particular memory cells is blocked. The circuit is used in a test structure for integrated circuits on a wafer. A method for testing integrated circuits on a wafer that are connected to a test apparatus is also described. Once the supply voltage to a first circuit to be tested has been turned on, a preliminary test is carried out to ascertain parameters that need to be set. The supply voltage is then applied to a next circuit to be tested, a preliminary test is carried out, and memory cells have information written to them, until the parameters have been set for all the connected circuits to be tested. The test apparatus then carries out the actual operational test in parallel for all the connected circuits to be tested.

公开(公告)号：US06826111B2

公开(公告)日：2004-11-30

申请号：US10186327

申请日：2002-06-28

申请人： Ralf Schneider ,  Evangelos Stavrou ,  Tobias Hartner ,  Norbert Wirth

发明人： Ralf Schneider ,  Evangelos Stavrou ,  Tobias Hartner ,  Norbert Wirth

IPC分类号： G11C800

CPC分类号： G11C29/36 ,  G11C29/18

摘要： A method includes providing a semiconductor memory device having at least one memory cell array. The memory cell array has a multiplicity of memory cells arranged in a matrix-like manner. Each of the memory cells is assigned a physical address and an electrical address. The method also includes inputting a physical address of a memory cell that is to be addressed into an address input device of the semiconductor memory device, decoding the input physical address into the assigned electrical address of the memory cell to be addressed by an address decoder device of the semiconductor memory device, and outputting the electrical address to the memory cell array in order to address the memory cell.

摘要翻译： 一种方法包括提供具有至少一个存储单元阵列的半导体存储器件。 存储单元阵列具有以矩阵状排列的多个存储单元。 每个存储单元被分配一个物理地址和一个电子地址。 该方法还包括将要寻址的存储器单元的物理地址输入到半导体存储器件的地址输入设备中，将输入物理地址解码为由地址解码器器件寻址的存储器单元的分配电地址 并且将电地址输出到存储单元阵列以便寻址存储单元。

公开(公告)号：US5537352A

公开(公告)日：1996-07-16

申请号：US339515

申请日：1994-11-14

申请人： Willibald Meyer ,  Norbert Wirth

发明人： Willibald Meyer ,  Norbert Wirth

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/409 ,  G11C11/4096 ,  G11C7/00

CPC分类号： G11C7/1087 ,  G11C11/4096 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1078

摘要： An integrated semiconductor memory configuration includes a memory region having a plurality of segments. Each of the memory region segments have a plurality of read amplifiers and bit lines. Each two of the bit lines are connected to a respective one of the read amplifiers. A plurality of parallel data lines lead to the memory region. Each of the data lines have an end oriented toward and another end oriented away from a respective one of the memory region segments. Each of a plurality of read/write amplifier switches is disposed at one of the ends of the respective data lines. Each of a plurality of selector switches connects the read/write amplifier switch disposed on the end of a respective one of the data lines oriented toward the memory region segment to a respective one of the read amplifiers of the memory region segment.

摘要翻译： 集成半导体存储器配置包括具有多个段的存储器区域。 每个存储器区段具有多个读取放大器和位线。 位线中的每一个连接到相应的一个读放大器。 多个并行数据线通向存储区域。 每个数据线具有朝向并且另一端朝向远离相应的一个存储器区段的端部。 多个读/写放大器开关中的每一个设置在相应数据线的一端。 多个选择器开关中的每一个将设置在朝向存储区域段的相应一个数据线的端部上的读/写放大器开关连接到存储器区段的读取放大器的相应一个。

公开(公告)号：US5329493A

公开(公告)日：1994-07-12

申请号：US74329

申请日：1993-06-09

申请人： Willibald Meyer ,  Norbert Wirth

发明人： Willibald Meyer ,  Norbert Wirth

IPC分类号： G09G5/00 ,  G09G5/36 ,  G11C7/10 ,  G11C11/401 ,  H04N5/907 ,  G11C13/00

CPC分类号： G11C7/1075 ,  G11C7/103

摘要： An integrated semiconductor memory array includes a memory region, a writing buffer memory associated with the memory region, a writing pointer and an input buffer associated with the writing buffer memory, a reading buffer memory associated with the memory region, a reading pointer and an output buffer associated with the reading buffer memory, and a control device being formed of a memory control circuit and a data flow control circuit. A reading column address decoder controlling the reading pointer is associated with the reading buffer memory. A reading address control unit is connected to the reading column address decoder, and a reading address register is connected to the reading address control unit. A writing column address decoder controlling the writing pointer is associated with the writing buffer memory. A writing address control unit is connected to the writing column address decoder, and a writing address register is connected to the writing address control unit. A line address decoder is provided in the memory control circuit or in the memory region and is triggerable by the reading address control unit and the writing address control unit.

摘要翻译： 集成半导体存储器阵列包括存储器区域，与存储器区域相关联的写入缓冲存储器，写入指针和与写入缓冲存储器相关联的输入缓冲器，与存储器区域相关联的读取缓冲存储器，读取指针和输出 与读取缓冲存储器相关联的缓冲器，以及由存储器控制电路和数据流控制电路构成的控制装置。 控制读取指针的读取列地址解码器与读取缓冲存储器相关联。 读取地址控制单元连接到读取列地址解码器，并且读取地址寄存器连接到读取地址控制单元。 控制写指针的写列地址解码器与写缓冲存储器相关联。 写入地址控制单元连接到写入列地址解码器，并且写入地址寄存器连接到写入地址控制单元。 行地址解码器设置在存储器控制电路或存储器区域中，并且可由读取地址控制单元和写入地址控制单元触发。

公开(公告)号：US06556486B2

公开(公告)日：2003-04-29

申请号：US09998725

申请日：2001-11-30

申请人： Herbert Benzinger ,  Norbert Wirth ,  Ralf Schneider

发明人： Herbert Benzinger ,  Norbert Wirth ,  Ralf Schneider

IPC分类号： G11O1604

CPC分类号： G11C7/1006 ,  G11C7/22

摘要： A circuit configuration and a method for the synchronization of signals include transmitting signals in parallel through data lines and buffer-storing the signals in a synchronizing unit. A clock signal is determined from the signals of a data line and is used for synchronizing the outputting of the signals. The signals are output in the order in which the signals were read. The signals are likewise output through a plurality of data lines, the signals being output temporally synchronously. Propagation time differences are compensated due to the buffer-storage. Moreover, the clock signal is determined from the signals themselves. Consequently, the use of an additional clock signal is not necessary.