公开(公告)号：US06426640B1

公开(公告)日：2002-07-30

申请号：US09440803

申请日：1999-11-15

申请人： Norbert Wirth ,  Eric Cordes ,  Zoltan Manyoki ,  Dominique Savignac

发明人： Norbert Wirth ,  Eric Cordes ,  Zoltan Manyoki ,  Dominique Savignac

IPC分类号： G01R3102

CPC分类号： G01R31/2856 ,  G01R31/2884

摘要： The invention relates to a semiconductor module for a burn-in test configuration. The semiconductor module has a regulator which, when it is turned on, always supplies a constant low voltage to an internal circuit of the semiconductor module. The semiconductor module also contains a component which, when the burn-in voltage has been applied for a defined time period, supplies a different characteristic than when the internal voltage is applied.

摘要翻译： 本发明涉及一种用于老化测试配置的半导体模块。 半导体模块具有调节器，当其导通时，总是向半导体模块的内部电路提供恒定的低电压。 半导体模块还包含当在已经施加了预定时间段的老化电压时提供与施加内部电压不同的特性的组件。

公开(公告)号：US06693447B1

公开(公告)日：2004-02-17

申请号：US09277281

申请日：1999-03-26

申请人： Dominique Savignac ,  Frank Weber ,  Norbert Wirth

发明人： Dominique Savignac ,  Frank Weber ,  Norbert Wirth

IPC分类号： G01R3126

CPC分类号： G01R31/2884

摘要： A configuration for identifying contact faults during the testing of integrated circuits with a multiplicity of pins which protrude from a housing and are connected to respective pads on a semiconductor body of the integrated circuit. Pull-up or pull-down devices are connected between respective pads and input buffers and in each case hold the pads at a high or low potential by impressing a holding current, if contact has not been made with a pin associated with the pad during testing, the result being that activation of the circuit section connected to the pin is avoided.

摘要翻译： 用于在具有从壳体突出并且连接到集成电路的半导体主体上的相应焊盘的多个引脚的集成电路测试期间识别接触故障的配置。 上拉或下拉器件连接在相应的焊盘和输入缓冲器之间，并且在每种情况下，通过施加保持电流来将焊盘保持在高或低电位，如果在测试期间没有与焊盘相关联的引脚进行接触 结果是避免了与引脚连接的电路部分的激活。

公开(公告)号：US5905687A

公开(公告)日：1999-05-18

申请号：US904500

申请日：1997-08-01

申请人： Rudiger Brede ,  Dominique Savignac ,  Norbert Wirth

发明人： Rudiger Brede ,  Dominique Savignac ,  Norbert Wirth

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/789

摘要： The fuse refresh circuit for semiconductor memories has a set circuit for setting a fuse latch circuit. The fuse latch circuit is set by the set circuit in at least one refresh cycle after a voltage supply has been switched on. During the refresh cycle of the fuse latch circuit, the latter is driven with pulses in such a way that the state of the fuse latch circuit is evaluated and only an incorrectly set fuse latch circuit is set to be correct.

摘要翻译： 半导体存储器的保险丝刷新电路具有用于设定熔丝锁存电路的设定电路。 熔断器锁存电路在电源接通之后至少在一个刷新周期内由设定电路设置。 在保险丝锁存电路的刷新周期期间，后者用脉冲驱动，使得对熔丝锁存电路的状态进行评估，并且仅将不正确设置的熔丝锁存电路设置为正确。

公开(公告)号：US08293431B2

公开(公告)日：2012-10-23

申请号：US12761876

申请日：2010-04-16

申请人： Haiko Rolff ,  Carla Byloos ,  Christoph Noelscher ,  Nicolo Morgana ,  Roderick Koehle ,  Molela Moukara ,  Ralf Neubauer ,  Rainer Pforr ,  Dominique Savignac

发明人： Haiko Rolff ,  Carla Byloos ,  Christoph Noelscher ,  Nicolo Morgana ,  Roderick Koehle ,  Molela Moukara ,  Ralf Neubauer ,  Rainer Pforr ,  Dominique Savignac

IPC分类号： G03F1/40

CPC分类号： G03F1/40 ,  G03F1/26 ,  G03F1/30 ,  G03F1/32

摘要： A lithographic mask comprises a first layer including grooves, a second layer including regions, sections and a groove-like structure that encloses the sections. The first and second layers are formed so as to reduce electrical potential differences within the second layer. A method of forming a lithographic mask includes forming first and second layers to dispose the second layer over the first layer, patterning the second layer to comprise sections, a region, and a groove-like structure enclosing the sections, and forming grooves in the first layer at portions not covered by the second layer. The first and second layers are formed to reduce potential differences within the second layers during the step of forming the grooves in the first layer.

摘要翻译： 平版印刷掩模包括包括凹槽的第一层，包含区域的第二层和包围区段的凹槽状结构。 形成第一层和第二层以便减小第二层内的电位差。 形成光刻掩模的方法包括形成第一层和第二层以将第二层设置在第一层上，将第二层图案化以包括封闭这些区段的区段，区域和沟槽状结构，以及在第一层中形成凹槽 层在未被第二层覆盖的部分。 形成第一层和第二层，以在形成第一层中的槽的步骤期间减小第二层内的电位差。

公开(公告)号：US07796446B2

公开(公告)日：2010-09-14

申请号：US12234312

申请日：2008-09-19

申请人： Hermann Ruckerbauer ,  Michael Bruennert ,  Ullrich Menczigar ,  Christian Mueller ,  Sitt Tontisirin ,  Georg Braun ,  Dominique Savignac

发明人： Hermann Ruckerbauer ,  Michael Bruennert ,  Ullrich Menczigar ,  Christian Mueller ,  Sitt Tontisirin ,  Georg Braun ,  Dominique Savignac

IPC分类号： G11C7/10

CPC分类号： G11C7/1048 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C29/70 ,  H01L2224/16145

摘要： A memory die, including a memory array, a memory array data terminal and a data bus that includes a first sub bus and a second sub bus is disclosed. A first bi-directional buffer arranged between the memory array data terminal and the first sub bus and a second bi-directional buffer arranged between the memory array data terminal and the second sub bus is also disclosed. The first and second bi-directional buffers are adapted to couple the first sub bus or the second sub bus to the memory array data terminal at a time.

摘要翻译： 公开了包括存储器阵列，存储器阵列数据终端和包括第一子总线和第二子总线的数据总线的存储器管芯。 还公开了布置在存储器阵列数据终端和第一子总线之间的第一双向缓冲器和布置在存储器阵列数据终端和第二副总线之间的第二双向缓冲器。 第一和第二双向缓冲器一次适于将第一子总线或第二子总线耦合到存储器阵列数据终端。

公开(公告)号：US07698470B2

公开(公告)日：2010-04-13

申请号：US11834617

申请日：2007-08-06

申请人： Hermann Ruckerbauer ,  Dominique Savignac

发明人： Hermann Ruckerbauer ,  Dominique Savignac

IPC分类号： G06F3/00 ,  H03K19/173 ,  H01L25/00

CPC分类号： G11C5/04 ,  G11C5/02 ,  G11C7/10 ,  G11C29/1201 ,  G11C2029/0407 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/00

摘要： An integrated circuit includes a first connection and a memory circuit. The integrated circuit is switchable between a master mode of operation, in which a buffer between the first connection and the memory circuit is activated, and a slave mode of operation, in which the buffer between the first connection and the memory circuit is deactivated.

摘要翻译： 集成电路包括第一连接和存储电路。 集成电路可以在其中第一连接和存储器电路之间的缓冲器被激活的主操作模式和从动操作模式之间切换，其中第一连接和存储器电路之间的缓冲器被停用。

公开(公告)号：US20090122628A1

公开(公告)日：2009-05-14

申请号：US12122273

申请日：2008-05-16

申请人： Dominique Savignac ,  Helmut Schneider

发明人： Dominique Savignac ,  Helmut Schneider

IPC分类号： G11C7/00

CPC分类号： H01L27/10897 ,  G11C11/4085 ,  G11C11/4094 ,  H01L27/0207 ,  H01L27/105

摘要： A device with a precharge/homogenize circuit. One embodiment provides at least one switching element is acting as a homogenizer, and at least one switching element is acting as a precharger. The diffusion region of the switching element acting as a homogenizer is separated from the diffusion region of the switching element acting as a precharger.

摘要翻译： 具有预充电/均质电路的器件。 一个实施例提供至少一个开关元件用作均化器，并且至少一个开关元件充当预充电器。 作为均化器的开关元件的扩散区域与作为预充电器的开关元件的扩散区域分离。

公开(公告)号：US20080217655A1

公开(公告)日：2008-09-11

申请号：US12028474

申请日：2008-02-08

申请人： Dirk Baumann ,  Dominique Savignac ,  Till Schloesser ,  Helmut Schneider

发明人： Dirk Baumann ,  Dominique Savignac ,  Till Schloesser ,  Helmut Schneider

IPC分类号： H01L29/76

CPC分类号： H01L27/10891

摘要： An integrated circuit with buried control line structures. In one embodiment, the control lines are subdivided into sections, wherein regions free of switching transistors are provided at intervals along the control lines. Connections for feeding the control potentials into the sections of the control lines are provided at least in a subset of the regions free of switching transistors. The isolations lines are connected to one another by an interconnect running transversely with respect to the control lines.

摘要翻译： 具有埋地控制线结构的集成电路。 在一个实施例中，控制线被细分为多个部分，其中不存在开关晶体管的区域沿着控制线间隔设置。 至少在没有开关晶体管的区域的子集中提供用于将控制电位馈送到控制线的部分中的连接。 隔离线通过相对于控制线横向运行的互连而彼此连接。

公开(公告)号：US20070033487A1

公开(公告)日：2007-02-08

申请号：US11182063

申请日：2005-07-15

申请人： Hermann Ruckerbauer ,  Dominique Savignac

发明人： Hermann Ruckerbauer ,  Dominique Savignac

IPC分类号： G11C29/00

CPC分类号： G11C7/1006 ,  G06F11/1052 ,  G11C29/42 ,  G11C2207/104

摘要： A semiconductor memory device including semiconductor memory cells with at least one memory cell capable of either acting as a storage device for ECC information or of acting as a redundant memory cell is provided. The semiconductor memory device further includes a signal control device for signaling if the at least one memory cell is to be used either as a storage device or as a redundant memory cell. A method of operating a semiconductor memory device is also provided including the steps of registering a status of a signal device and, depending on the status of the signal device, operating the at least one memory cell either as a storing device for ECC information or as a redundant memory cell.

摘要翻译： 提供一种半导体存储器件，其包括具有至少一个存储单元的半导体存储单元，所述至少一个存储单元可以充当用于ECC信息的存储器件或用作冗余存储器单元。 半导体存储器件还包括信号控制装置，用于发信号通知至少一个存储单元是作为存储装置还是用作冗余存储单元。 还提供了一种操作半导体存储器件的方法，包括以下步骤：注册信号器件的状态，并且根据信号器件的状态，操作至少一个存储器单元作为ECC信息的存储设备或者作为 冗余存储单元。

公开(公告)号：US06816432B2

公开(公告)日：2004-11-09

申请号：US10146582

申请日：2002-05-15

申请人： Robert Feurle ,  Dominique Savignac

发明人： Robert Feurle ,  Dominique Savignac

IPC分类号： G11C800

CPC分类号： H01L27/10873 ,  H01L21/823462 ,  H01L27/10894 ,  H01L27/10897

摘要： It is known to adapt the dimensions of transistors, in particular a layer thickness of a local gate oxide in a manner dependent on an operating voltage. Therefore, semiconductor circuits having transistors with different operating voltages are provided with transistors having gate oxides of different thicknesses. This allows the gate oxide thickness to be influenced even more extensively. In this case, account is taken of the fact that infrequently addressed transistors, in particular memory transistors given the same gate oxide thickness, have a significantly longer lifetime than frequently switched transistors. An integrated semiconductor circuit having transistors whose gate oxide thicknesses are adapted to the switching frequency having different magnitudes, is proposed.

摘要翻译： 已知以取决于工作电压的方式适应晶体管的尺寸，特别是局部栅极氧化物的层厚度。 因此，具有不同工作电压的晶体管的半导体电路设置有具有不同厚度的栅极氧化物的晶体管。 这允许栅极氧化物厚度更广泛地影响。 在这种情况下，考虑到这样一个事实，即不常寻址的晶体管，特别是赋予相同栅极氧化物厚度的存储器晶体，具有比频率切换晶体管显着更长的寿命。 提出了具有栅极氧化物厚度适应于具有不同幅度的开关频率的晶体管的集成半导体电路。