公开(公告)号：US6090523A

公开(公告)日：2000-07-18

申请号：US54885

申请日：1998-04-03

申请人： Norihiko Samoto ,  Haruo Iwasaki ,  Atsushi Nishizawa ,  Tsuyoshi Yoshii ,  Hiroshi Yoshino

发明人： Norihiko Samoto ,  Haruo Iwasaki ,  Atsushi Nishizawa ,  Tsuyoshi Yoshii ,  Hiroshi Yoshino

IPC分类号： G03F7/11 ,  C08L25/18 ,  C08L33/02 ,  C08L33/12 ,  C08L61/06 ,  C08L79/08 ,  G02B1/11 ,  G02B1/111 ,  G03F7/09 ,  H01L21/027 ,  G03C1/76

CPC分类号： G03F7/091

摘要： An antireflection film includes a base resin and an additive resin, the additive resin having a dry etching rate higher than that of the base resin. A photoresist pattern is formed and the antireflection film is selectively etched using the photoresist pattern as a mask. The molecular weight and weight percent of the additive resin are selected to provide an etching rate for the antireflection film that permits selective removal of the antireflection film while leaving an effective amount of the photoresist.

摘要翻译： 防反射膜包括基础树脂和添加剂树脂，添加剂树脂的干蚀刻速率高于基础树脂。 形成光致抗蚀剂图案，并使用光致抗蚀剂图案作为掩模选择性地蚀刻防反射膜。 选择添加剂树脂的分子量和重量百分数以提供防反射膜的蚀刻速率，其允许选择性去除防反射膜，同时留下有效量的光致抗蚀剂。

公开(公告)号：US06864021B2

公开(公告)日：2005-03-08

申请号：US10341160

申请日：2003-01-13

申请人： Haruo Iwasaki ,  Shinji Ishida ,  Tsuyoshi Yoshii

发明人： Haruo Iwasaki ,  Shinji Ishida ,  Tsuyoshi Yoshii

IPC分类号： G03F1/00 ,  G03F1/68 ,  G03F1/70 ,  G03F7/20 ,  G03F7/40 ,  H01L21/027 ,  H01L21/28 ,  H01L21/311 ,  G03F9/00

CPC分类号： G03F7/40 ,  G03F1/00 ,  H01L21/31144

摘要： The invention relates to a photomask for use in a thermal flow process in which: a photomask is prepared in which a plurality of exposure openings are formed; a resist is applied to the surface of a layer of a semiconductor integrated circuit that is to undergo processing; this resist is patterned by an exposure process through the photomask to form a plurality of openings in the resist that correspond to each of the exposure openings; and the patterned resist is then heated to cause each of the openings to shrink; wherein at least a portion of exposure openings among the plurality of exposure openings are formed in shapes that compensate for anisotropic deformation that occurs in the openings when the patterned resist is heated to cause each of the openings to shrink. Since the openings that are formed in the resist are provided in advance with shapes that compensate for the deformation that occurs when the openings shrink, these openings attain the proper shape after undergoing shrinking and deformation.

摘要翻译： 本发明涉及一种用于热流程的光掩模，其中：准备形成多个曝光孔的光掩模; 将抗蚀剂施加到要进行处理的半导体集成电路的层的表面上; 该抗蚀剂通过曝光工艺通过光掩模进行图案化以在抗蚀剂中形成与每个曝光开口相对应的多个开口; 然后加热图案化的抗蚀剂以使每个开口收缩; 其中所述多个曝光开口中的所述曝光开口的至少一部分形成为补偿当所述图案化抗蚀剂被加热以使每个所述开口收缩时在所述开口中发生的各向异性变形的形状。 由于在抗蚀剂中形成的开口预先设置有补偿当开口收缩时发生的变形的形状，所以这些开口在经历收缩和变形之后达到适当的形状。

公开(公告)号：US06566041B2

公开(公告)日：2003-05-20

申请号：US09757841

申请日：2001-01-10

申请人： Haruo Iwasaki ,  Shinji Ishida ,  Tsuyoshi Yoshii

发明人： Haruo Iwasaki ,  Shinji Ishida ,  Tsuyoshi Yoshii

IPC分类号： G03F740

CPC分类号： G03F7/40 ,  G03F1/00 ,  H01L21/31144

摘要： The invention relates to a photomask for use in a thermal flow process in which: a photomask is prepared in which a plurality of exposure openings are formed; a resist is applied to the surface of a layer of a semiconductor integrated circuit that is to undergo processing; this resist is patterned by an exposure process through the photomask to form a plurality of openings in the resist that correspond to each of the exposure openings; and the patterned resist is then heated to cause each of the openings to shrink; wherein at least a portion of exposure openings among the plurality of exposure openings are formed in shapes that compensate for anisotropic deformation that occurs in the openings when the patterned resist is heated to cause each of the openings to shrink. Since the openings that are formed in the resist are provided in advance with shapes that compensate for the deformation that occurs when the openings shrink, these openings attain the proper shape after undergoing shrinking and deformation.

摘要翻译： 本发明涉及一种用于热流程的光掩模，其中：准备形成多个曝光孔的光掩模; 将抗蚀剂施加到要进行处理的半导体集成电路的层的表面上; 该抗蚀剂通过曝光工艺通过光掩模进行图案化以在抗蚀剂中形成与每个曝光开口相对应的多个开口; 然后加热图案化的抗蚀剂以使每个开口收缩; 其中所述多个曝光开口中的所述曝光开口的至少一部分形成为补偿当所述图案化抗蚀剂被加热以使每个所述开口收缩时在所述开口中发生的各向异性变形的形状。 由于在抗蚀剂中形成的开口预先设置有补偿当开口收缩时发生的变形的形状，所以这些开口在经历收缩和变形之后达到适当的形状。

公开(公告)号：US06524945B2

公开(公告)日：2003-02-25

申请号：US10132213

申请日：2002-04-26

申请人： Haruo Iwasaki

发明人： Haruo Iwasaki

IPC分类号： H01L214763

CPC分类号： H01L21/0276 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/3144 ,  H01L21/32139 ,  H01L21/76897 ,  H01L27/10873 ,  Y10S438/952

摘要： An anti-reflection structure formed on a gate electrode in a MOSFET device includes a first and second anti-reflection layers sandwiching therebetween a silicon nitride layer. Each of the anti-reflection layers has a two-layer structure including a silicon oxide nitride film and a protective silicon oxide film. The anti-reflection layer structure improves the accuracy of the pattern size for the gate electrode.

摘要翻译： 形成在MOSFET器件的栅电极上的防反射结构包括在其间夹着氮化硅层的第一和第二抗反射层。 每个防反射层具有包括氧化硅氮化物膜和保护氧化硅膜的两层结构。 抗反射层结构提高了栅电极的图案尺寸的精度。

公开(公告)号：US06274427B1

公开(公告)日：2001-08-14

申请号：US09551198

申请日：2000-04-17

申请人： Haruo Iwasaki

发明人： Haruo Iwasaki

IPC分类号： H01L218242

CPC分类号： H01L27/10855 ,  H01L21/76895 ,  H01L27/10814 ,  H01L28/87

摘要： A capacitor is provided, which makes it easy to increase the opposing area size between the lower and upper electrode in spite of miniaturization, and which ensures a desired capacitance value large enough for stable operation of a semiconductor memory device in spite of miniaturization. The capacitor is comprised of a lower electrode formed over an interlayer dielectric layer of a substrate, an upper electrode, and a dielectric located between the lower and upper electrodes. The lower electrode has a first electrode part and a second electrode part connected to each other. The first electrode part includes a plate-shaped bottom subpart and a sidewall subpart extending upward from the periphery of the bottom subpart. The bottom subpart and the sidewall subpart form an inner space. At least part of the second electrode part is located in the inner space so that a first gap is formed between the bottom subpart and the second electrode part and a second gap is formed between the sidewall subpart and the second electrode part. The upper electrode is opposed to the bottom subpart of the first electrode part of the lower electrode and to the second electrode part thereof in the first gap, and is opposed to the sidewall subpart of the first electrode part of the lower electrode and to the second electrode part thereof in the second gap.

摘要翻译： 提供了一种电容器，这使得即使小型化，也容易增加下电极和上电极之间的相对面积尺寸，并且尽管小型化而确保半导体存储器件的稳定操作足够大的期望电容值。 电容器由在基板的层间电介质层上形成的下电极，上电极和位于下电极和上电极之间的电介质构成。 下电极具有彼此连接的第一电极部分和第二电极部分。 第一电极部分包括从底部子部分的周边向上延伸的板状底部部分和侧壁子部分。 底部子部分和侧壁子部分形成内部空间。 第二电极部分的至少一部分位于内部空间中，使得在底部部分和第二电极部分之间形成第一间隙，并且在侧壁部分和第二电极部分之间形成第二间隙。 上电极与下电极的第一电极部分的底部子部分和第一间隙中的第二电极部分相对，并且与下电极的第一电极部分的侧壁子部分相对，并且与第二电极部分的第二电极部分相对 电极部分在第二间隙中。

公开(公告)号：US06200845B1

公开(公告)日：2001-03-13

申请号：US09553172

申请日：2000-04-20

申请人： Haruo Iwasaki

发明人： Haruo Iwasaki

IPC分类号： H01L218242

CPC分类号： H01L28/91 ,  H01L27/10852

摘要： The present invention provides a method of forming at least a bottom electrode of a capacitor in a semiconductor device. The method comprises the steps forming a first insulation film on a multilayer structure over a semiconductor substrate; forming at least a contact hole which penetrates through the first insulation film and the multilayer structure to reach a surface of the semiconductor substrate; selectively removing the first insulation film to form mask patterns on the multilayer structure; forming a single conductive film which extends within the at least contact hole and over the multilayer structure as well as cover the mask patterns; forming a second insulation film on the single conductive film; partially removing the second insulation film and the single conductive film over the mask patterns so that tops of the mask patterns are shown; and removing remaining parts of the second insulation film and the mask patterns to form at least a bottom electrode comprising a single conductive layer.

摘要翻译： 本发明提供一种在半导体器件中形成电容器的至少底部电极的方法。 该方法包括在半导体衬底上的多层结构上形成第一绝缘膜的步骤; 至少形成穿过所述第一绝缘膜和所述多层结构的接触孔，以到达所述半导体衬底的表面; 选择性地去除所述第一绝缘膜以在所述多层结构上形成掩模图案; 形成在所述至少接触孔内并在所述多层结构上延伸的单个导电膜以及覆盖所述掩模图案; 在单个导电膜上形成第二绝缘膜; 在掩模图案上部分地去除第二绝缘膜和单个导电膜，以示出掩模图案的顶部; 以及去除第二绝缘膜和掩模图案的剩余部分以形成至少包括单个导电层的底部电极。

公开(公告)号：US5907772A

公开(公告)日：1999-05-25

申请号：US806420

申请日：1997-02-26

申请人： Haruo Iwasaki

发明人： Haruo Iwasaki

IPC分类号： H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： The invention relates to the fabrication of a cylindrical storage node in a stacked capacitor cell of DRAM. As is usual, a MOS transistor is fabricated in a silicon substrate, and interlayer insulator and interconnection are formed on the substrate. As an upper interlayer insulator film which serves as an etch stop film, a silicon nitride or silicon oxide film is formed, and this film is overlaid with a planarizing film such as a BPSG film. Then, a contact hole is formed and filled with a conductor to provide a storage node contact. After that the planarizing film is removed, and a cylindrical storage node is formed on the exposed etch stop film. The cylindrical part of the storage node is formed by patterning a relatively thick BPSG film so as to provide a cylindrical wall face, forming a polysilicon sidewall on the cylindrical wall face and then completely removing the BPSG film. At this stage the etch stop film retains sufficient thickness since this film was protected by the planarizing film at the stage of forming the storage node contact. So, no defects such as cavities develop in interlayer insulators. By this method the total thickness of interlayer insulators can be reduced, so that the storage node contact can be formed accurately and reliably.

摘要翻译： 本发明涉及DRAM的层叠电容器单元中的圆柱形存储节点的制造。 通常，在硅衬底中制造MOS晶体管，并且在衬底上形成层间绝缘体和互连。 作为用作蚀刻停止膜的上层绝缘膜，形成氮化硅或氧化硅膜，并且用BPSG膜等平坦化膜覆盖该膜。 然后，形成接触孔并填充导体以提供存储节点接触。 之后去除平坦化膜，并且在暴露的蚀刻停止膜上形成圆柱形存储节点。 存储节点的圆柱形部分通过对相对较厚的BPSG膜进行图案化而形成，以提供圆柱形壁面，在圆柱形壁面上形成多晶硅侧壁，然后完全去除BPSG膜。 在这个阶段，蚀刻停止膜保持足够的厚度，因为该膜在形成存储节点接触的阶段由平坦化膜保护。 因此，在层间绝缘体中不会出现空洞等缺陷。 通过这种方法，可以减少层间绝缘体的总厚度，从而可以准确可靠地形成存储节点接触。

公开(公告)号：US06841318B2

公开(公告)日：2005-01-11

申请号：US10277512

申请日：2002-10-22

申请人： Haruo Iwasaki

发明人： Haruo Iwasaki

IPC分类号： G03F1/30 ,  G03F1/36 ,  G03F1/68 ,  H01L21/027 ,  G03F9/00

CPC分类号： G03F1/30 ,  G03F1/36 ,  G03F1/70

摘要： Levenson masks capable of minimizing the effect of optical proximity, and a method for forming a fine pattern using such Levenson masks wherein the Levenson masks have patterns where shielding regions are sandwiched between shifter regions and non-shifter regions respectively. The shifter regions and the non-shifter regions are formed to have predetermined shapes to minimize the effect of optical proximity. Specifically, aperture widths, which are defined as widths of the shifter regions and widths of the non-shifter regions perpendicular to the longitudinal directions of the linear shielding regions, are of a predetermined width for minimizing the effect of optical proximity. The Levenson masks have patterns different from each other and are used for multiple exposures.

摘要翻译： 能够使光学接近效果最小化的列文生掩模，以及使用这种利文森掩模形成精细图案的方法，其中莱文森掩模具有分别在移动区域和非移动区域之间夹着屏蔽区域的图案。 移位器区域和非移位器区域形成为具有预定形状以最小化光学接近的影响。 具体地，定义为移动区域的宽度和垂直于线性屏蔽区域的纵向方向的非移动区域的宽度的孔径宽度是用于使光学邻近效应最小化的预定宽度。 莱文森面具具有彼此不同的图案，用于多次曝光。

公开(公告)号：US06525353B1

公开(公告)日：2003-02-25

申请号：US09689881

申请日：2000-10-13

申请人： Haruo Iwasaki

发明人： Haruo Iwasaki

IPC分类号： H01L2976

CPC分类号： H01L21/0276 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/3144 ,  H01L21/32139 ,  H01L21/76897 ,  H01L27/10873 ,  Y10S438/952

摘要： An anti-reflection structure formed on a gate electrode in a MOSFET device includes a first and second anti-reflection layers sandwiching therebetween a silicon nitride layer. Each of the anti-reflection layers has a two-layer structure including a silicon oxide nitride film and a protective silicon oxide film. The anti-reflection layer structure improves the accuracy of the pattern size for the gate electrode.

公开(公告)号：US06200853B1

公开(公告)日：2001-03-13

申请号：US09414051

申请日：1999-10-07

申请人： Haruo Iwasaki

发明人： Haruo Iwasaki

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L21/76816 ,  H01L27/10855 ,  H01L28/60

摘要： A method of manufacturing a semiconductor device having capacitor contact holes. The method comprises: forming a first insulating film to cover the gate electrode and the source/drain electrodes; forming a second insulating film on the first insulating film; forming a third insulating film made of material different from that of the second insulating film on the second insulating film; forming a first resist film on the third insulating film; patterning the first resist film by using a first exposure mask to form a patterned first resist film; selectively removing the third insulating film by using the patterned first resist film as a mask; forming a second resist film to cover the patterned first resist film; patterning the second resist film by using a second exposure mask to form a patterned second resist film; selectively removing the first and second insulating films on at least a portion of one of the source/drain regions in each of the element forming regions by using the patterned first and second resist films as a mask to form capacitor contact holes; and forming a conductive film to fill the capacitor contact holes.

摘要翻译： 一种制造具有电容器接触孔的半导体器件的方法。 该方法包括：形成第一绝缘膜以覆盖栅电极和源/漏电极; 在所述第一绝缘膜上形成第二绝缘膜; 在所述第二绝缘膜上形成由与所述第二绝缘膜不同的材料制成的第三绝缘膜; 在所述第三绝缘膜上形成第一抗蚀剂膜; 通过使用第一曝光掩模来图案化第一抗蚀剂膜以形成图案化的第一抗蚀剂膜; 通过使用图案化的第一抗蚀剂膜作为掩模来选择性地去除第三绝缘膜; 形成第二抗蚀剂膜以覆盖图案化的第一抗蚀剂膜; 通过使用第二曝光掩模来图案化第二抗蚀剂膜以形成图案化的第二抗蚀剂膜; 通过使用图案化的第一和第二抗蚀剂膜作为掩模，在每个元件形成区域中的源极/漏极区域中的一个的至少一部分上选择性地去除第一和第二绝缘膜，以形成电容器接触孔; 并形成导电膜以填充电容器接触孔。