公开(公告)号：US06594717B2

公开(公告)日：2003-07-15

申请号：US10237113

申请日：2002-09-09

申请人： Norman J. Rasmussen ,  Brad W. Hosler ,  Darren Abramson ,  Michael J. McTague

发明人： Norman J. Rasmussen ,  Brad W. Hosler ,  Darren Abramson ,  Michael J. McTague

IPC分类号： G06F1300

CPC分类号： G06F13/385

摘要： Apparatus and methods to control an external bus. In one embodiment, an apparatus includes an external bus port and an external bus controller. The external bus controller can include a first register interface to receive a first set of data and a second register interface to receive a second set of data. The external bus controller can send the first set of data and the second set of data to said external bus port.

公开(公告)号：US06502146B1

公开(公告)日：2002-12-31

申请号：US09537087

申请日：2000-03-29

申请人： Norman J. Rasmussen ,  Brad W. Hosler ,  Darren Abramson ,  Michael J. McTague

发明人： Norman J. Rasmussen ,  Brad W. Hosler ,  Darren Abramson ,  Michael J. McTague

IPC分类号： G06F1300

CPC分类号： G06F13/385

摘要： Apparatus and methods to control an external bus. In one embodiment, an apparatus includes an external bus port and an external bus controller. The external bus controller can include a first register interface to receive a first set of data and a second register interface to receive a second set of data. The external bus controller can send the first set of data and the second set of data to said external bus port.

摘要翻译： 控制外部总线的装置和方法。 在一个实施例中，装置包括外部总线端口和外部总线控制器。 外部总线控制器可以包括用于接收第一组数据的第一寄存器接口和用于接收第二组数据的第二寄存器接口。 外部总线控制器可以将第一组数据和第二组数据发送到所述外部总线端口。

公开(公告)号：US07620833B2

公开(公告)日：2009-11-17

申请号：US11633183

申请日：2006-12-04

申请人： Chai Huat Gan ,  Darren Abramson ,  Zohar Bogin

发明人： Chai Huat Gan ,  Darren Abramson ,  Zohar Bogin

IPC分类号： G06F1/32

CPC分类号： G06F1/3225

摘要： For isochronous data steams processed by a computer system, for example high definition audio streams, embodiments keep track of the free space available in the input and output buffers for the data streams. The available free space in the buffers determines whether various low power entry and exit thresholds are met or not. If all low power entry thresholds are met, then various circuits such as clocks, phase locked loops, and direct media interface links, may be put into a low power state, and the data stream controller enters an idle window so that memory requests are not serviced. During this time, system DRAM may begin refresh. Once the low power state has been entered into, if any exit threshold is met, then the low power state is ended. Other embodiments are described and claimed.

摘要翻译： 对于由计算机系统处理的等时数据流，例如高清晰度音频流，实施例跟踪用于数据流的输入和输出缓冲器中的可用空间。 缓冲器中的可用空间确定是否满足各种低功率进入和退出阈值。 如果满足所有低功率入口阈值，则诸如时钟，锁相环和直接介质接口链路的各种电路可能被置于低功率状态，并且数据流控制器进入空闲窗口，使得存储器请求不是 服务。 在此期间，系统DRAM可能会开始刷新。 一旦输入低功率状态，如果满足任何退出阈值，则低功率状态结束。 描述和要求保护其他实施例。

公开(公告)号：US06473843B2

公开(公告)日：2002-10-29

申请号：US09776221

申请日：2001-02-02

申请人： Darren Abramson ,  Joseph Bennett

发明人： Darren Abramson ,  Joseph Bennett

IPC分类号： G06F1200

CPC分类号： G06F1/30

摘要： The present invention relates to a method and apparatus for restoring a status data in a computer system. The circuit comprises: a read-only register for storing a read-only status value during a normal mode of operation; a first data path for supplying the read-only status value; a first control signal path for supplying a first control signal for controlling writing the supplied read-only status value into the read-only register during the normal mode of operation, the stored read-only status value being saved into a save area prior to removing power from the read-only register; a second data path for subsequently resupplying from the save area the previously stored read-only status value; a second control signal path for supplying a second control signal for controlling restoration of the re-supplied read-only status value into the read-only register during a restore mode of operation; and circuitry coupling the first and second data and control signal paths to the read-only register to facilitate the writing during the normal mode of operation and the restoration during the restore mode of operation.

摘要翻译： 本发明涉及一种在计算机系统中恢复状态数据的方法和装置。 该电路包括：只读寄存器，用于在正常操作模式期间存储只读状态值; 用于提供只读状态值的第一数据路径; 第一控制信号路径，用于在正常操作模式期间提供用于控制将提供的只读状态值写入只读寄存器的第一控制信号，将所存储的只读状态值保存到保存区域中，然后再移除 只读寄存器的电源; 第二数据路径，用于随后从保存区域重新提供先前存储的只读状态值; 第二控制信号路径，用于在恢复操作模式期间提供用于控制再提供的只读状态值恢复到只读寄存器的第二控制信号; 以及将第一和第二数据和控制信号路径耦合到只读寄存器的电路，以便于在恢复操作模式期间的正常操作模式和恢复期间的写入。

公开(公告)号：US09424211B2

公开(公告)日：2016-08-23

申请号：US12347970

申请日：2008-12-31

申请人： Zohar Bogin ,  Suryaprasad Kareenahaili ,  Rajeev K. Nalawadi ,  Michael Tabet ,  Darren Abramson

发明人： Zohar Bogin ,  Suryaprasad Kareenahaili ,  Rajeev K. Nalawadi ,  Michael Tabet ,  Darren Abramson

IPC分类号： G06F9/455 ,  G06F13/24 ,  G06F9/48

CPC分类号： G06F13/24 ,  G06F9/45533 ,  G06F9/45558 ,  G06F9/4812

摘要： Embodiments of apparatuses, methods, and systems for providing multiple virtual device controllers by redirecting an interrupt from a physical device controller are disclosed. In one embodiment, an apparatus includes a processor, a physical device controller, and virtualization logic. The virtualization logic is to receive a first interrupt from the physical device controller, and in response, send a second interrupt to the processor from one of a plurality of virtual device controllers.

摘要翻译： 公开了通过从物理设备控制器重定向中断来提供多个虚拟设备控制器的设备，方法和系统的实施例。 在一个实施例中，装置包括处理器，物理设备控制器和虚拟化逻辑。 虚拟化逻辑是从物理设备控制器接收第一中断，并且作为响应，从多个虚拟设备控制器之一向处理器发送第二中断。

公开(公告)号：US5951667A

公开(公告)日：1999-09-14

申请号：US778192

申请日：1997-01-02

申请人： Darren Abramson

发明人： Darren Abramson

IPC分类号： G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4036

摘要： Modern personal computers often have several internal buses. An integrated expansion bus bridge is disclosed that couples to a fast main computer bus and couples several different expansion buses to the fast main computer bus. In one personal computer embodiment, the fast main computer bus bus is the Peripheral Component Interconnect (PCI) Bus. The expansion bus bridge obains control of the PCI bus and then arbitrates the bus control among several entities requesting access to the PCI bus. In one personal computer embodiments, the entities requesting access to the PCI bus include a Universal Serial Bus (USB) controller, an Industry Standard Architecture (ISA) bus controller, and an Integrated Drive Electronics controller. To prevent deadlock situations, the integrated expansion bus controller passively releases the PCI Bus when an ISA Direct Memory Access (DMA) operation is in progress. A passive release of the PCI bridge prevents CPU postings to or behind the expansion bus bridge from occurring. If no ISA DMA operation is in progress, then the expansion bus bridge may actively release the PCI bus.

摘要翻译： 现代个人电脑通常有几辆内部公交车。 公开了一种集成的扩展总线桥，其耦合到快速主计算机总线，并将几个不同的扩展总线耦合到快速主计算机总线。 在一个个人计算机实施例中，快速主计算机总线总线是外围组件互连（PCI）总线。 扩展总线桥控制PCI总线，然后在请求访问PCI总线的几个实体之间仲裁总线控制。 在一个个人计算机实施例中，请求访问PCI总线的实体包括通用串行总线（USB）控制器，工业标准架构（ISA）总线控制器和集成驱动电子控制器。 为了防止死锁情况，当ISA直接存储器访问（DMA）操作正在进行时，集成扩展总线控制器被动地释放PCI总线。 PCI桥的被动释放可防止发生扩展总线桥之后或之后的CPU发布。 如果没有ISA DMA操作正在进行，则扩展总线桥可以主动释放PCI总线。

公开(公告)号：US5857117A

公开(公告)日：1999-01-05

申请号：US577866

申请日：1995-12-22

申请人： Darren Abramson ,  Joe A. Bennett

发明人： Darren Abramson ,  Joe A. Bennett

IPC分类号： G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4022

摘要： A transceiver as provided for effectively multiplexing IDE address and data lines with selected ISA address and data lines. Compatibility among the IDE data transfers and ISA functions are achieved by multiplexing the ISA lines that do not involve the ISA refresh of the ISA expanded memory. The transceiver includes an enable input that, when disabled, effectively isolates the IDE data lines from the ISA bus so that IDE data transfers can occur. When the enable input is active, the ISA lines not related to refresh are connected to the IDE data lines so that ISA operations can occur. Furthermore, a directional input is included in the transceiver for allowing a central processing unit to control the ISA when the directional input is active and for allowing a PCI/ISA bridge between the PCI bus and the ISA bus to control the ISA operations included the multiplexing. The result is a rearrangement of the IDE data lines with the ISA bus to eliminate a multitude of pins and connectors.

摘要翻译： 提供的收发器，用于有效地复用IDE地址和数据线与选定的ISA地址和数据线。 IDE数据传输和ISA功能之间的兼容性是通过复用不涉及ISA扩展内存的ISA刷新的ISA线来实现的。 收发器包括一个使能输入，当被禁用时，有效地将IDE数据线与ISA总线隔离，以便可以发生IDE数据传输。 当启用输入处于活动状态时，与刷新无关的ISA线路连接到IDE数据线，以便可以进行ISA操作。 此外，收发器中包括方向输入，用于当方向输入有效时允许中央处理单元控制ISA，并允许PCI总线与ISA总线之间的PCI / ISA桥控制包括复用的ISA操作 。 结果是IDE数据线与ISA总线重新排列，以消除大量的引脚和连接器。

公开(公告)号：US20080133952A1

公开(公告)日：2008-06-05

申请号：US11633183

申请日：2006-12-04

申请人： Chai Huat Gan ,  Darren Abramson ,  Zohar Bogin

发明人： Chai Huat Gan ,  Darren Abramson ,  Zohar Bogin

IPC分类号： G06F13/00 ,  G06F1/32

CPC分类号： G06F1/3225

摘要： For isochronous data steams processed by a computer system, for example high definition audio streams, embodiments keep track of the free space available in the input and output buffers for the data streams. The available free space in the buffers determines whether various low power entry and exit thresholds are met or not. If all low power entry thresholds are met, then various circuits such as clocks, phase locked loops, and direct media interface links, may be put into a low power state, and the data stream controller enters an idle window so that memory requests are not serviced. During this time, system DRAM may begin refresh. Once the low power state has been entered into, if any exit threshold is met, then the low power state is ended. Other embodiments are described and claimed.

摘要翻译： 对于由计算机系统处理的等时数据流，例如高清晰度音频流，实施例跟踪用于数据流的输入和输出缓冲器中的可用空间。 缓冲器中的可用空间确定是否满足各种低功率进入和退出阈值。 如果满足所有低功率入口阈值，则诸如时钟，锁相环和直接介质接口链路的各种电路可能被置于低功率状态，并且数据流控制器进入空闲窗口，使得存储器请求不是 服务。 在此期间，系统DRAM可能会开始刷新。 一旦输入低功率状态，如果满足任何退出阈值，则低功率状态结束。 描述和要求保护其他实施例。

公开(公告)号：US20070233909A1

公开(公告)日：2007-10-04

申请号：US11395678

申请日：2006-03-30

申请人： Michael Derr ,  Darren Abramson ,  Bryan Doucette ,  Karthi Vadivelu

发明人： Michael Derr ,  Darren Abramson ,  Bryan Doucette ,  Karthi Vadivelu

IPC分类号： G06F3/00 ,  G06F13/14

CPC分类号： G06F1/3203 ,  G06F1/3253 ,  Y02D10/151 ,  Y02D50/20

摘要： A method, apparatus, and system to synchronize multiple host controllers with non-uniform frame rates. The apparatus includes a first host controller, a second host controller, and logic. The first host controller is configured to access memory at a first frame rate. The second host controller is configured to access the memory at a second frame rate which is different from the first frame rate. The logic is coupled to the first and second host controllers to synchronize the memory accesses of the first and second host controllers at a common frame rate. Other embodiments are described.

摘要翻译： 一种以非均匀帧速率同步多个主机控制器的方法，装置和系统。 该装置包括第一主机控制器，第二主机控制器和逻辑。 第一主机控制器被配置为以第一帧速率访问存储器。 第二主机控制器被配置为以与第一帧速率不同的第二帧速率访问存储器。 该逻辑耦合到第一和第二主机控制器以以公共帧速率同步第一和第二主机控制器的存储器访问。 描述其他实施例。

公开(公告)号：US6000043A

公开(公告)日：1999-12-07

申请号：US672872

申请日：1996-06-28

申请人： Darren Abramson

发明人： Darren Abramson

IPC分类号： G06F11/267 ,  G06F11/273

CPC分类号： G06F11/221 ,  G06F11/2221

摘要： A method and apparatus for operating a peripheral system having one or more peripheral devices coupled to at least one bus is described. When a bus master initiates a transaction with a peripheral device that ends in an abort condition (such as a Master Abort condition in a PCI architecture), the bus master generates an interrupt (such as the System Management Interrupt) to a central processing unit (CPU). When the interrupt is received, the CPU then attempts to determine the cause of the abort condition. For example, if the peripheral device is operating in a low power consumption mode, the CPU attempts to power up the device so that a retry of the transaction will be successful. Since the peripheral devices can be kept in a low power consumption mode until accessed by a bus master, the power consumption for the computer system is greatly reduced.

摘要翻译： 描述了用于操作具有耦合到至少一个总线的一个或多个外围设备的外围系统的方法和装置。 当总线主机与终止于中止状态（例如PCI架构中的主机中止条件）的外围设备发起交易时，总线主机向中央处理单元（例如系统管理中断）产生中断（例如系统管理中断） 中央处理器）。 当接收到中断时，CPU然后尝试确定中止条件的原因。 例如，如果外围设备工作在低功耗模式，CPU会尝试启动设备，以便重试事务将成功。 由于外围设备可以保持在低功耗模式，直到总线主机访问，所以计算机系统的功耗大大降低。