公开(公告)号：US06657244B1

公开(公告)日：2003-12-02

申请号：US10195596

申请日：2002-06-28

申请人： Omer H. Dokumaci ,  Bruce B. Doris ,  Robert J. Purtell

发明人： Omer H. Dokumaci ,  Bruce B. Doris ,  Robert J. Purtell

IPC分类号： H01L2976

CPC分类号： H01L29/66507 ,  H01L29/66545

摘要： A method of fabricating a semiconductor structure where a low gate resistance is obtained, while simultaneously reducing silicon consumption in the source/drain diffusion regions. The method provides a semiconductor structure having a thin silicide region formed atop source/drain regions and a thicker silicide region formed atop gate regions. The method includes: first forming a structure which includes self-aligned silicide regions atop the source/drain diffusion regions and the gate region. A non-reactive film and a planarizing film are then applied to the structure containing the self-aligned silicide regions and thereafter a thicker silicide region, as compared to the self-aligned silicide region located atop the source/drain regions, is formed on the gate region.

摘要翻译： 一种制造半导体结构的方法，其中获得低栅极电阻，同时降低源极/漏极扩散区域中的硅消耗。 该方法提供了半导体结构，其具有形成在源极/漏极区顶部的薄硅化物区域和形成在栅极区域顶部的较厚硅化物区域。 该方法包括：首先在源极/漏极扩散区域和栅极区域顶部形成包括自对准硅化物区域的结构。 然后将非反应性膜和平坦化膜施加到包含自对准硅化物区域的结构，然后与位于源极/漏极区域顶部的自对准硅化物区域相比较，形成较厚的硅化物区域 门区域。

公开(公告)号：US20080246090A1

公开(公告)日：2008-10-09

申请号：US12119765

申请日：2008-05-13

申请人： Omer H. Dokumaci ,  Bruce B. Doris ,  Kathryn W. Guarini ,  Suryanarayan G. Hegde ,  MeiKei Ieong ,  Erin Catherine Jones

发明人： Omer H. Dokumaci ,  Bruce B. Doris ,  Kathryn W. Guarini ,  Suryanarayan G. Hegde ,  MeiKei Ieong ,  Erin Catherine Jones

IPC分类号： H01L27/12

CPC分类号： H01L29/78648 ,  H01L21/0338 ,  H01L21/2007 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/42384

摘要： A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer; a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.

摘要翻译： 提供了具有横向排列的前（上）和后门的双栅极晶体管。 双栅晶体管包括在器件层下面的背栅热氧化层; 位于背栅极氧化物层下面的背栅电极; 位于器件层上方的前门热氧化物; 前栅极热氧化物上方的前栅极电极层，并与背栅电极垂直对准; 以及设置在背栅极热氧化物层上方的与第一栅极对称的晶体管体。 背栅电极具有形成在晶体管本体下方和在背栅电极的中心部分的任一侧上的氧化物层，从而将后栅极与前栅极自对准。 晶体管还包括在所述晶体管体的相对侧上的源极和漏极。

公开(公告)号：US07271446B2

公开(公告)日：2007-09-18

申请号：US10916814

申请日：2004-08-12

申请人： Omer H. Dokumaci ,  Bruce B. Doris

发明人： Omer H. Dokumaci ,  Bruce B. Doris

IPC分类号： H01L27/01

CPC分类号： H01L29/66772 ,  H01L21/2255 ,  H01L29/6656 ,  H01L29/78621

摘要： The inventive method for forming thin channel MOSFETS comprises: providing a structure including at least a substrate having a layer of semiconducting material atop an insulating layer and a gate region formed atop the layer of semiconducting material; forming a conformal oxide film atop the structure; implanting the conformal oxide film; forming a set of spacers atop the conformal oxide film, said set of sidewall spacers are adjacent to the gate region; removing portions of the oxide film, not protected by the set of spacers to expose a region of the semiconducting material; forming raised source/drain regions on the exposed region of the semiconducting material; implanting the raised source/drain regions with a second dopant impurity to form a second dopant impurity region; and annealing a final structure to provide a thin channel MOSFET.

摘要翻译： 用于形成薄沟道MOSFET的本发明的方法包括：提供至少包括在绝缘层顶部具有半导体材料层的衬底和形成在半导体材料层顶上的栅极区域的结构的结构; 在结构顶部形成保形氧化膜; 植入保形氧化膜; 在所述共形氧化物膜的上方形成一组间隔物，所述一组侧壁间隔物邻近所述栅极区; 去除未被所述一组间隔物保护的氧化膜的部分以暴露所述半导体材料的区域; 在所述半导体材料的暴露区域上形成凸起的源极/漏极区域; 用第二掺杂杂质注入凸起的源/漏区以形成第二掺杂杂质区; 并退火最终结构以提供薄沟道MOSFET。

公开(公告)号：US06977194B2

公开(公告)日：2005-12-20

申请号：US10695752

申请日：2003-10-30

申请人： Michael P. Belyansky ,  Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Bruce B. Doris ,  Oleg Gluschenkov

发明人： Michael P. Belyansky ,  Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Bruce B. Doris ,  Oleg Gluschenkov

IPC分类号： H01L21/20 ,  H01L21/28 ,  H01L21/302 ,  H01L21/336 ,  H01L21/44 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/72 ,  H01L29/78 ,  H01L29/786 ,  H01L31/062

CPC分类号： H01L29/7845 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/785

摘要： In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nFET and pFET), carrier mobility is enhanced or otherwise regulated through the reacting the material of the gate electrode with a metal to produce a stressed alloy (preferably CoSi2, NiSi, or PdSi) within a transistor gate. In the case of both the nFET and pFET, the inherent stress of the respective alloy results in an opposite stress on the channel of respective transistor. By maintaining opposite stresses in the nFET and pFET alloys or silicides, both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.

摘要翻译： 在制造包括nFET和pFET的互补金属氧化物半导体（CMOS）场效应晶体管的情况下，通过使栅电极的材料与金属反应来增强或调节载流子迁移率，以产生应力合金（优选CoSi 2Si，NiSi或PdSi）。 在nFET和pFET两者的情况下，各合金的固有应力对相应晶体管的沟道产生相反的应力。 通过在nFET和pFET合金或硅化物中保持相反的应力，单个芯片或衬底上的两种类型的晶体管可以实现增强的载流子迁移率，从而提高CMOS器件和集成电路的性能。

公开(公告)号：US06667197B1

公开(公告)日：2003-12-23

申请号：US10314499

申请日：2002-12-06

申请人： Oleg Gluschenkov ,  Bruce B. Doris ,  Omer H. Dokumaci

发明人： Oleg Gluschenkov ,  Bruce B. Doris ,  Omer H. Dokumaci

IPC分类号： H01L2100

CPC分类号： H01L21/823842 ,  H01L21/823864

摘要： A method of forming a substantially uniform oxide film over surfaces with different level of doping and/or different dopant type is disclosed. In one aspect, a method for forming a uniform oxide spacer on the sidewalls of heavily doped n- and p-type gates is disclosed. The method includes providing a semiconductor substrate having at least two regions with dissimilar dopant characteristics, optionally heating the substrate; and forming a uniform oxide layer over the at least two regions by exposing the substrate to a gaseous mixture including atomic oxygen.

摘要翻译： 公开了在具有不同掺杂水平和/或不同掺杂剂类型的表面上形成基本上均匀的氧化膜的方法。 一方面，公开了在重掺杂的n型和p型栅极的侧壁上形成均匀的氧化物间隔物的方法。 该方法包括提供具有至少两个具有不同掺杂特性的区域的半导体衬底，可选地加热衬底; 以及通过将所述衬底暴露于包括原子氧的气体混合物，在所述至少两个区域上形成均匀的氧化物层。

公开(公告)号：US06645867B2

公开(公告)日：2003-11-11

申请号：US09864974

申请日：2001-05-24

申请人： Omer H. Dokumaci ,  Bruce B. Doris

发明人： Omer H. Dokumaci ,  Bruce B. Doris

IPC分类号： H01L21301

CPC分类号： H01L21/31144 ,  H01L21/3185 ,  H01L21/76224 ,  H01L21/76283

摘要： Disclosed is a method of protecting a semiconductor shallow trench isolation (STI) oxide from etching, the method comprising lowering, if necessary, the upper surface of said STI oxide to a level below that of adjacent silicon active areas, depositing a nitride liner upon said STI oxide and adjacent silicon active areas in a manner effective in defining a depression above said STI oxide, filling said depression with a protective film, and removing said nitride layer from said adjacent active areas.

公开(公告)号：US07453123B2

公开(公告)日：2008-11-18

申请号：US11676030

申请日：2007-02-16

申请人： Omer H. Dokumaci ,  Bruce B. Doris ,  Kathryn W. Guarini ,  Suryanarayan G. Hegde ,  Meikei Ieong ,  Erin Catherine Jones

发明人： Omer H. Dokumaci ,  Bruce B. Doris ,  Kathryn W. Guarini ,  Suryanarayan G. Hegde ,  Meikei Ieong ,  Erin Catherine Jones

IPC分类号： H01L27/01

CPC分类号： H01L29/78648 ,  H01L21/0338 ,  H01L21/2007 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/42384

摘要： A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer: a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.

摘要翻译： 提供了具有横向排列的前（上）和后门的双栅极晶体管。 双栅晶体管包括在器件层下面的背栅热氧化层; 位于背栅极氧化物层下面的背栅电极; 在器件层上方的前栅极热氧化物：位于前栅极热氧化物上方并与背栅电极垂直对准的前栅极电极层; 以及设置在所述背栅极热氧化物层上方的与所述第一栅极对称的晶体管体。 背栅电极具有形成在晶体管本体下方和在背栅电极的中心部分的任一侧上的氧化物层，从而将后栅极与前栅极自对准。 晶体管还包括在所述晶体管体的相对侧上的源极和漏极。

公开(公告)号：US07205185B2

公开(公告)日：2007-04-17

申请号：US10663471

申请日：2003-09-15

申请人： Omer H. Dokumaci ,  Bruce B. Doris ,  Kathryn W. Guarini ,  Suryanarayan G. Hegde ,  MeiKei Ieong ,  Erin Catherine Jones

发明人： Omer H. Dokumaci ,  Bruce B. Doris ,  Kathryn W. Guarini ,  Suryanarayan G. Hegde ,  MeiKei Ieong ,  Erin Catherine Jones

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/78648 ,  H01L21/0338 ,  H01L21/2007 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/42384

摘要： A double-gate transistor has front (upper) and back gates aligned laterally by a process of forming symmetric sidewalls in proximity to the front gate and then oxidizing the back gate electrode at a temperature of at least 1000 degrees for a time sufficient to relieve stress in the structure, the oxide penetrating from the side of the transistor body to thicken the back gate oxide on the outer edges, leaving an effective thickness of gate oxide at the center, aligned with the front gate electrode. Optionally, an angled implant from the sides of an oxide enhancing species encourages relatively thicker oxide in the outer implanted areas and an oxide-retarding implant across the transistor body retards oxidation in the vertical direction, thereby permitting increase of the lateral extent of the oxidation.

摘要翻译： 双栅极晶体管具有通过在前栅极附近形成对称侧壁然后在至少1000度的温度下氧化背栅电极足以缓解应力的时间的方法横向排列的前（上）和后门 在该结构中，氧化物从晶体管主体的侧面渗透，以增厚外边缘上的背栅氧化层，留下中心的栅极氧化物的有效厚度，与前栅电极对准。 任选地，来自氧化物增强物质的侧面的成角度的植入物鼓励外部注入区域中相对较厚的氧化物，并且跨越晶体管体的氧化物延迟植入阻碍垂直方向上的氧化，从而允许增加氧化的横向范围。

公开(公告)号：US06806534B2

公开(公告)日：2004-10-19

申请号：US10342423

申请日：2003-01-14

申请人： Omer H. Dokumaci ,  Bruce B. Doris ,  Oleg Gluschenkov ,  Jack A. Mandelman ,  Carl J. Radens

发明人： Omer H. Dokumaci ,  Bruce B. Doris ,  Oleg Gluschenkov ,  Jack A. Mandelman ,  Carl J. Radens

IPC分类号： H01L2976

CPC分类号： H01L29/66583 ,  H01L21/26586 ,  H01L21/28114 ,  H01L29/665 ,  H01L29/66553

摘要： A MOSFET fabrication methodology and device structure, exhibiting improved gate activation characteristics. The gate doping that may be introduced while the source drain regions are protected by a damascene mandrel to allow for a very high doping in the gate conductors, without excessively forming deep source/drain diffusions. The high gate conductor doping minimizes the effects of electrical depletion of carriers in the gate conductor. The MOSFET fabrication methodology and device structure further results in a device having a lower gate conductor width less than the minimum lithographic minimum image, and a wider upper gate conductor portion width which may be greater than the minimum lithographic image. Since the effective channel length of the MOSFET is defined by the length of the lower gate portion, and the line resistance is determined by the width of the upper gate portion, both short channel performance and low gate resistance are satisfied simultaneously.

摘要翻译： MOSFET制造方法和器件结构，表现出改进的栅极激活特性。 当源极漏极区域被镶嵌心轴保护以允许栅极导体中的非常高的掺杂而不会过度地形成深的源极/漏极扩散时，可以引入栅极掺杂。 高栅极导体掺杂最大限度地减小了栅极导体中载流子的电耗损的影响。 MOSFET制造方法和器件结构进一步导致具有小于最小光刻最小图像的较低栅极导体宽度的器件，以及可能大于最小光刻图像的较宽上部栅极导体部分宽度。 由于MOSFET的有效沟道长度由下栅极部分的长度限定，并且线路电阻由上部栅极部分的宽度决定，所以同时满足短沟道性能和低栅极电阻。

公开(公告)号：US06803315B2

公开(公告)日：2004-10-12

申请号：US10212938

申请日：2002-08-05

申请人： Omer H. Dokumaci ,  Bruce B. Doris

发明人： Omer H. Dokumaci ,  Bruce B. Doris

IPC分类号： H01L21302

CPC分类号： H01L29/66545 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/312 ,  H01L21/3144 ,  H01L21/31612 ,  H01L21/3185

摘要： A method is provided for blocking implants from the gate electrode of an FET device. Form a first planarizing film covering the substrate and the gate electrode stack. The first planarizing film is planarized by either polishing or self-planarizing. For deposition by HDP or use of spin on materials, the film is self-planarizing. Where polishing is required, the first planarizing film is planarized by polishing until the top of the gate electrode is exposed. Etch back the gate electrode below the level of the upper surface of the first planarizing film. Then deposit a blanket layer of a second planarizing film and polish to planarize it to a level exposing the first planarizing film, forming the second planarizing film into an implantation block covering the top surface of the gate. Remove the first planarizing film. Form the counterdoped regions by implanting dopant into the substrate using the implantation block to block implantation of the dopant into the gate electrode. The implantation block protects the gate electrode of the FET from unwanted implanted impurities during implanting of the counterdoped regions. The first planarizing film is composed of a material selected from the group consisting of HDP (high density plasma) silicon oxide and HDP silicon nitride, an interlevel-dielectric layer material including ONO, and photoresist. The gate electrode is composed of a material selected from the group consisting of polysilicon and metal. The second planarizing film comprises a material such as HDP oxide, HDP nitride, and an organic layer including ARCs. The second planarizing film comprises a different material from the first planarizing film.

摘要翻译： 提供了一种用于阻挡来自FET器件的栅电极的植入物的方法。 形成覆盖基板和栅极电极堆叠的第一平坦化膜。 第一平面化膜通过抛光或自平面平坦化。 为了通过HDP沉积或者在材料上使用旋涂，该膜是自平面化的。 在需要抛光的情况下，第一平面化膜通过抛光进行平坦化，直到栅电极的顶部露出。 在第一平面化膜的上表面的水平面下方蚀刻栅电极。 然后沉积第二平坦化膜和抛光剂的覆盖层以将其平坦化至暴露第一平坦化膜的水平，将第二平坦化膜形成为覆盖栅极顶表面的注入块。 取下第一个平面化膜。 通过使用注入块将掺杂剂注入衬底来形成反向掺杂区域，以阻止掺杂剂注入到栅电极中。 注入块在植入反向掺杂区域期间保护FET的栅电极免受不希望的注入杂质。 第一平面化膜由选自HDP（高密度等离子体）氧化硅和HDP氮化硅的材料，包含ONO的层间介电层材料和光致抗蚀剂组成。 栅电极由选自多晶硅和金属的材料组成。 第二平面化膜包括诸如HDP氧化物，HDP氮化物和包括ARC的有机层的材料。 第二平面化膜包括与第一平坦化膜不同的材料。