公开(公告)号：US5629700A

公开(公告)日：1997-05-13

申请号：US552016

申请日：1995-11-02

申请人： Toshio Kumamoto ,  Osamu Matsumoto ,  Takahiro Miki ,  Masao Ito ,  Takashi Okuda

发明人： Toshio Kumamoto ,  Osamu Matsumoto ,  Takahiro Miki ,  Masao Ito ,  Takashi Okuda

IPC分类号： H03M1/14 ,  H03M1/00 ,  H03M1/06 ,  H03M1/12 ,  H03M1/16 ,  H03M1/44 ,  H03M1/34

CPC分类号： H03M1/002 ,  H03M1/0682 ,  H03M1/069 ,  H03M1/1215 ,  H03M1/167

摘要： An A/D converter block A/D1 converts an analog input signal Vin to a digital signal and outputs its D/A output. First SH/SUBT7, 8 sample the signal Vin and a voltage VRM at the same timing with said A/D conversion and output the results of subtraction of the respective sampling values and the D/A output during holding, respectively. The both results of subtraction are several tens mV and there is no need of taking account of the linearity of a differential amplifier DIFF11. During the sampling, a circuit SHR1 outputs the differential voltages between each reference tap voltage taken out from specific 2 points of the ladder-type resistor in the A/D converter block A/D1 and the voltage VRM while a differential amplifier DIFF12 applies the reference voltages to the next A/D converter block A/D2. Such operations are performed in each stage. Thus, it becomes possible to make any S/H circuit and amplifier of excellent linearity in the first stage unnecessary to reduce the electric power consumption.

摘要翻译： A / D转换器模块A / D1将模拟输入信号Vin转换为数字信号并输出​​其D / A输出。 第一SH / SUBT7,8以与所述A / D转换相同的定时采样信号Vin和电压VRM，并分别输出相应采样值和保持期间的D / A输出的结果。 减法的结果都是几十mV，不需要考虑差分放大器DIFF11的线性度。 在采样期间，电路SHR1输出从A / D转换器模块A / D1中的梯形电阻器的特定2点取出的每个参考分接电压与电压VRM之间的差分电压，而差分放大器DIFF12施加参考 电压到下一个A / D转换器模块A / D2。 这样的操作在每个阶段进行。 因此，可以使得在第一级中具有优异线性度的任何S / H电路和放大器不必减少电力消耗。

公开(公告)号：US5995031A

公开(公告)日：1999-11-30

申请号：US968207

申请日：1997-11-12

申请人： Takashi Okuda ,  Toshio Kumamoto ,  Masao Ito ,  Takahiro Miki

发明人： Takashi Okuda ,  Toshio Kumamoto ,  Masao Ito ,  Takahiro Miki

IPC分类号： H03M1/10 ,  H03M1/06 ,  H03M1/74 ,  H03M1/66

CPC分类号： H03M1/0663 ,  H03M1/747 ,  H03M3/464 ,  H03M3/502

摘要： A multi-bit D/A converter which improves the linearity of an analog output relative to a digital input is provided. A switch control circuit (1) turns on D some of a plurality of switches (S1 to SM) which are arranged in ascending order starting with a switch determined by a start position determination circuit (3) and turns off the remaining switches, the number of switches turned on being dependent on a digital signal (DIG). The start position determination circuit (3) sequentially changes the switches (S1, S3, S5, . . . ) serving as a selection start position to determine the selection start position for each input of the digital signal (DIG) provided in synchronism with a clock signal (CLK).

摘要翻译： 提供了一种提高模拟输出相对于数字输入的线性度的多位D / A转换器。 开关控制电路（1）接通D开始的开关位置确定电路（3）确定的开关的升序排列的多个开关（S1至SM）中的一些，并且关闭其余的开关 开关依赖于数字信号（DIG）。 开始位置确定电路（3）顺序地改变用作选择开始位置的开关（S1，S3，S5 ...），以确定与设置的与数字信号（DIG）同步的数字信号（DIG）的每个输入的选择开始位置 时钟信号（CLK）。

公开(公告)号：US5936434A

公开(公告)日：1999-08-10

申请号：US912813

申请日：1997-08-19

申请人： Toshio Kumamoto ,  Masao Ito ,  Takahiro Miki ,  Takashi Okuda

发明人： Toshio Kumamoto ,  Masao Ito ,  Takahiro Miki ,  Takashi Okuda

IPC分类号： H03M1/34 ,  H03F3/45 ,  H03K5/08 ,  H03K5/24 ,  H03K5/153

CPC分类号： H03K5/249 ,  H03K5/2481

摘要： An object is to obtain a voltage comparator capable of high-accuracy voltage comparison. An input voltage (VIN) and a reference voltage (VREF) are connected to one electrode of a capacitor (C1) through switches (S1) and (S2), respectively. The other electrode of the capacitor (C1) is connected to the input portion of an inverter (INV1). The output portion of the inverter (INV1) is connected to the input portion of an inverter (INV3) and is also fed back to the input through a switch (S3). An inverter (INV11) is further connected in parallel with the inverter (INV1), wherein the input/output characteristics of the inverters (INV1, INV3 and INV11) are set equal.

摘要翻译： 目的是获得能够进行高精度电压比较的电压比较器。 分别通过开关（S1）和（S2）将输入电压（VIN）和参考电压（VREF）连接到电容器（C1）的一个电极。 电容器（C1）的另一个电极连接到逆变器（INV1）的输入部分。 逆变器（INV1）的输出部分连接到逆变器（INV3）的输入部分，并通过开关（S3）反馈到输入端。 反相器（INV11）进一步与反相器（INV1）并联连接，其中反相器（INV1，INV3和INV11）的输入/输出特性被设定为相等。

公开(公告)号：US06069579A

公开(公告)日：2000-05-30

申请号：US131238

申请日：1998-08-07

申请人： Masao Ito ,  Takeshi Shigenobu ,  Toshio Kumamoto ,  Takahiro Miki ,  Hiroshi Komurasaki

发明人： Masao Ito ,  Takeshi Shigenobu ,  Toshio Kumamoto ,  Takahiro Miki ,  Hiroshi Komurasaki

IPC分类号： H03M1/14 ,  H03M1/20 ,  H03M1/36 ,  H03M1/12

CPC分类号： H03M1/205 ,  H03M1/141

摘要： An A/D converter simplifies its circuit configuration without deteriorating accuracy in A/D conversion. A circuit is formed of a folding and interpolation type. A gain-variable pre-amplifier group 11 amplifies each of reference voltages Vref1 to VrefN and an analog input voltage Vin, to output the result to a folding amplifier group 12, while a gain-variable pre-amplifier group 21 amplifies each of reference voltages Vrr1 to VrrJ and the analog input voltage Vin, to output the result to a comparator group 24. Each of pre-amplifiers constituting the gain-variable pre-amplifier groups 11 and 21 has an amplification factor that varies in upper and lower comparison periods according to a clock control signal .PHI.cnt.

摘要翻译： A / D转换器简化了其电路配置，而不会降低A / D转换的精度。 电路由折叠和内插形式组成。 增益可变前置放大器组11放大每个参考电压Vref1至VrefN和模拟输入电压Vin，以将结果输出到折叠放大器组12，而增益可变的前置放大器组21放大每个参考电压 Vrr1至VrrJ和模拟输入电压Vin，将结果输出到比较器组24.构成增益可变前置放大器组11和21的每个前置放大器具有在上和下比较周期内变化的放大系数， 到时钟控制信号PHI cnt。

公开(公告)号：US06232804B1

公开(公告)日：2001-05-15

申请号：US09413751

申请日：1999-10-06

申请人： Takeshi Shigenobu ,  Masao Ito ,  Toshio Kumamoto

发明人： Takeshi Shigenobu ,  Masao Ito ,  Toshio Kumamoto

IPC分类号： G11C2702

CPC分类号： G11C27/026

摘要： In a sample hold circuit (6, 50, 60) capable of relaxing a dependency of a voltage of an analogue input signal on an ON resistance of a switch (2). In the sample hold circuit (6, 50, 60), plural reference voltages VrefN are supplied, and unit switches (11e) forming the switch (2) are selectively activated (an ON state) based on a comparison results (whether or not the voltage of the analogue input signal is greater than each reference voltage) from plural comparison circuits (13e) whose operations are performed based on the voltage of the analogue input signal (1).

摘要翻译： 在能够放松模拟输入信号的电压对开关（2）的导通电阻的依赖性的采样保持电路（6,50,60）中。 在采样保持电路（6,50,60）中，提供多个参考电压VrefN，并且基于比较结果（形成开关（2））的单元开关（11e）是否被选择性地激活（ON状态） 根据模拟输入信号（1）的电压执行其操作的多个比较电路（13e），模拟输入信号的电压大于每个参考电压）。

公开(公告)号：US5818380A

公开(公告)日：1998-10-06

申请号：US824549

申请日：1997-03-25

申请人： Masao Ito ,  Takahiro Miki ,  Shiro Hosotani

发明人： Masao Ito ,  Takahiro Miki ,  Shiro Hosotani

IPC分类号： H03M1/10 ,  H03K19/23 ,  H03M1/06 ,  H03M1/36

CPC分类号： H03M1/0602 ,  H03M1/361

摘要： A majority logic circuit is supplied with output values of adjacent three comparators. The majority logic circuit outputs, as an output signal, the supplied three output values including at least two equal output values. Inverter circuits and AND circuits produce and output a read signal of an encoder which is a logical product between the output signal and an inverted signal of the output signal.

摘要翻译： 多数逻辑电路提供相邻三个比较器的输出值。 多数逻辑电路作为输出信号输出所提供的三个输出值，包括至少两个相等的输出值。 逆变器电路和AND电路产生并输出编码器的读取信号，该编码器是输出信号和输出信号的反相信号之间的逻辑积。

公开(公告)号：US5497120A

公开(公告)日：1996-03-05

申请号：US350030

申请日：1994-11-29

申请人： Masao Ito ,  Takahiro Miki

发明人： Masao Ito ,  Takahiro Miki

IPC分类号： G01R19/165 ,  H03F1/30 ,  H03F3/45 ,  H03K17/16

CPC分类号： G01R19/16519 ,  H03F1/303 ,  H03F3/45076

摘要： A differential amplifier circuit is obtained in which an operating power source voltage is suppressed to a minimum necessary level. The differential amplifier circuit includes a bias circuit having a differential amplifier with NMOS transistors (11A, 11B, 12A and 12B) and PMOS transistors (13A and 13B). Sources of NMOS transistors (11A)and (11B) are commonly grounded. A bias voltage (VB1) is supplied to gates of the NMOS transistors (11A) and (11B). Drains of the NMOS transistors (11A) and (11B) are connected to sources of NMOS transistors (12A) and (12B), respectively. A gate and a drain of the NMOS transistor (12A) are short-circuited to each other with the drain connected to a drain of a PMOS transistor (13A). A bias voltage (VB4) is applied to a gate of the NMOS transistor (12B). A drain of the NMOS transistor (12B) is connected to a drain of the PMOS transistor (13B) whose gate and drain are shared by each other. Gates of the PMOS transistors (13A) and (13B) are connected to a bias terminal (72) while sources of the PMOS transistors (13A) and (13B) are commonly connected to a power source. The bias terminal (72) is connected to an input bias terminal of a differential amplifier.

摘要翻译： 获得了将工作电源电压抑制到最小必要水平的差分放大电路。 差分放大器电路包括具有NMOS晶体管（11A，11B，12A和12B）和PMOS晶体管（13A和13B）的差分放大器的偏置电路。 NMOS晶体管（11A）和（11B）的源极通常接地。 偏置电压（VB1）被提供给NMOS晶体管（11A）和（11B）的栅极。 NMOS晶体管（11A）和（11B）的漏极分别连接到NMOS晶体管（12A）和（12B）的源极。 NMOS晶体管（12A）的栅极和漏极彼此短路，漏极连接到PMOS晶体管（13A）的漏极。 偏置电压（VB4）施加到NMOS晶体管（12B）的栅极。 NMOS晶体管（12B）的漏极连接到其栅极和漏极彼此共享的PMOS晶体管（13B）的漏极。 PMOS晶体管（13A）和（13B）的栅极连接到偏置端子（72），而PMOS晶体管（13A）和（13B）的源极共同连接到电源。 偏置端子（72）连接到差分放大器的输入偏置端子。

公开(公告)号：US5225837A

公开(公告)日：1993-07-06

申请号：US706834

申请日：1991-05-29

申请人： Shiro Hosotani ,  Takahiro Miki ,  Masao Ito

发明人： Shiro Hosotani ,  Takahiro Miki ,  Masao Ito

IPC分类号： H03M1/36 ,  H03M1/78

CPC分类号： H03M1/362

摘要： An A/D converter includes a resistor network generating a reference voltage, a level detector for detecting the level of an input analogue signal with a reference voltage from the resistor network as a reference, and an encoder for providing a digital signal by encoding the output of the level detector. The level detector includes a plurality of comparators for bilevel-processing the input analogue signal with a preselected voltage from the resistor connection nodes of the resistor network as a reference voltage. The resistor network comprises a plurality of resistor elements between a first node receiving a first reference voltage and a second node receiving a second reference voltage, which are interconnected to provide a voltage from an associated connection node that is 1/2.sup.j times the difference between said first reference voltage and said second reference voltage. The comparator includes capacitors for providing the difference between the input analogue signal and the reference voltage by a capacitor coupling, and an inverter amplifier for determining the positive or negative of the voltage change generated by the capacitors. This structure implements an A/D converter of high precision with less elements.

摘要翻译： A / D转换器包括产生参考电压的电阻网络，用于以来自电阻器网络的参考电压作为参考来检测输入模拟信号的电平的电平检测器，以及用于通过对输出进行编码来提供数字信号的编码器 的电平检测器。 电平检测器包括多个比较器，用于以来自电阻器网络的电阻器连接节点的预选电压作为参考电压对输入的模拟信号进行二维处理。 电阻网络包括在接收第一参考电压的第一节点和接收第二参考电压的第二节点之间的多个电阻器元件，其互连以提供来自相关联的连接节点的电压，所述相关联的连接节点是所述 第一参考电压和所述第二参考电压。 比较器包括用于通过电容器耦合提供输入模拟信号和参考电压之间的差异的电容器，以及用于确定由电容器产生的电压变化的正或负的反相放大器。 该结构实现了具有较低元件精度的A / D转换器。

公开(公告)号：US5218247A

公开(公告)日：1993-06-08

申请号：US762560

申请日：1991-09-18

申请人： Masao Ito ,  Takahiro Miki

发明人： Masao Ito ,  Takahiro Miki

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H03K19/00

CPC分类号： H03K19/0013

摘要： A semiconductor integrated circuit includes a complementary MIS circuit including first PMIS and NMIS transistors with their drain electrodes connected together. The integrated circuit further includes a driving level-shift which includes a second PMIS transistor having its drain electrode grounded, and having its source electrode connected to the gate of the first PMIS transistor and to a V.sub.DD voltage supply terminal via a first resistor. The level-shift circuit further includes a second NMIS transistor having its drain electrode connected directly to the V.sub.DD voltage supply terminal, having its source electrode grounded via a second resistor, and having its gate electrode connected to the gate electrode of the second PMIS transistor. An input voltage is applied to the gate electrodes of the second PMIS and NMIS transistors.

摘要翻译： 半导体集成电路包括互补MIS电路，其包括第一PMIS和NMIS晶体管，其漏电极连接在一起。 集成电路还包括驱动电平转换，其包括其漏极接地的第二PMIS晶体管，并且其源极连接到第一PMIS晶体管的栅极，并经由第一电阻连接到VDD电压源端。 电平移位电路还包括第二NMIS晶体管，其漏极电极直接连接到VDD电压源端子，其源极通过第二电阻器接地，并且其栅电极连接到第二PMIS晶体管的栅电极。 输入电压施加到第二PMIS和NMIS晶体管的栅电极。

公开(公告)号：US5315301A

公开(公告)日：1994-05-24

申请号：US976056

申请日：1992-11-13

申请人： Shiro Hosotani ,  Takahiro Miki ,  Masao Ito

发明人： Shiro Hosotani ,  Takahiro Miki ,  Masao Ito

IPC分类号： H03M1/08 ,  H03M1/06 ,  H03M1/36

CPC分类号： H03M1/0643 ,  H03M1/068 ,  H03M1/361

摘要： An improved parallel-type A/D converter is disclosed, which includes encoder 3 constituted by a pseudo-NMOS type ROM, and encoder 28 constituted by a pseudo-PMOS type ROM. These encoders are connected to the outputs of pre-encoder 2. Averaging circuit 29 receives binary data provided from two encoders to provide average value data of these as converted binary output data. Even in case of multi-addressing, an averaging circuit can provide correct data as converted data. As a result, an A/D converter which is not affected by noise or the like has been obtained.

摘要翻译： 公开了一种改进的并行型A / D转换器，其包括由伪NMOS型ROM构成的编码器3和由伪PMOS型ROM构成的编码器28。 这些编码器连接到预编码器2的输出。平均电路29接收从两个编码器提供的二进制数据，以将它们的平均值数据提供为转换的二进制输出数据。 即使在多寻址的情况下，平均电路也可以提供作为转换数据的正确数据。 结果，已经获得了不受噪声等影响的A / D转换器。