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公开(公告)号：US20190130973A1
公开(公告)日：2019-05-02
申请号：US16233351
申请日：2018-12-27
Applicant: Pragmatic Printing LTD.
Inventor： Richard Price , Catherine Ramsdale
Abstract: A method of manufacturing an electronic circuit comprises: providing an electronic circuit having a first configuration in which the circuit comprises a resistive element having a first resistance, and irradiating at least a part of the resistive element with electromagnetic radiation to change the resistance of the resistive element from the first resistance to a second resistance, the second resistance being lower than the first resistance. A method of storing data comprises: receiving a piece of data to be stored; determining a number according to the data; and irradiating at least part of a resistive element with that number of pulses of electromagnetic radiation to change a resistance of the resistive element from a first resistance to a second resistance, the second resistance being lower than the first resistance. A difference between the first resistance and the second resistance is dependent on the number. Corresponding circuits and data storage systems are disclosed.
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公开(公告)号：US09768782B2
公开(公告)日：2017-09-19
申请号：US14905737
申请日：2014-07-16
Applicant: Pragmatic Printing Ltd
Inventor： Joao de Oliveira , Scott Darren White , Catherine Ramsdale
CPC classification number: H03K19/0944 , H03K3/0315 , H03K3/037 , H03K3/356017 , H03K17/16 , H03K19/09441 , H03K19/20 , H03K23/002
Abstract: An electronic circuit comprises: an input terminal; an output terminal; first and second supply rails; first, second, third, and fourth field effect transistors, FETs, each of a first type and each having respective gate, source and drain terminals; and first and second loads. The source of the first FET is connected to the first supply rail, the drain of the first FET and the source of the second FET are connected to the output terminal, the drain of the second FET is connected to the second supply rail, the gate of the third FET and the gate of the fourth FET are connected to the input terminal, the drain of the third FET is connected to the second supply rail, the first load is connected between the first supply rail and the source of the third FET, and the second load is connected between the drain of the fourth FET and the second supply rail. In one aspect of the invention, the gate of the first FET is connected to a node between the source of the third FET and the first load such that a voltage at the source of the third FET is applied to the gate of the first FET, and the gate of the second FET is connected to a node between the drain of the fourth FET and the second load such that a voltage at the drain of the fourth FET is applied to the gate of the second FET.
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公开(公告)号：US11004875B2
公开(公告)日：2021-05-11
申请号：US16497636
申请日：2018-03-27
Applicant: PRAGMATIC PRINTING LTD.
Inventor： Richard Price , Catherine Ramsdale , Brian Hardy Cobb , Feras Alkhalil
IPC: H01L27/12 , H01L21/02 , H01L21/027 , H01L21/285 , H01L21/306 , H01L21/3213 , H01L29/40 , H01L29/417
Abstract: A structure is disclosed, comprising: a first field effect transistor, FET, comprising a first source terminal, a first drain terminal, a first layer or body of semiconductive material arranged to provide a first semiconductive channel connecting the first source terminal to the first drain terminal, and a gate terminal arranged with respect to the first semiconductive channel such that a conductivity of the first semiconductive channel may be controlled by application of a voltage to the gate terminal; and a second FET comprising a second source terminal, a second drain terminal, a second layer or body of semiconductive material arranged to provide a second semiconductive channel connecting the second source terminal to the second drain terminal, and the gate terminal, the second conductive channel being arranged with respect to the gate terminal such that a conductivity of the second channel may be controlled by application of a voltage to the gate terminal. Methods of manufacturing such structures are also disclosed.
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公开(公告)号：US20170125249A1
公开(公告)日：2017-05-04
申请号：US15369159
申请日：2016-12-05
Applicant: Pragmatic Printing Ltd.
Inventor： Richard Price , Catherine Ramsdale
IPC: H01L21/268 , H01L51/00 , H01L21/428 , H01L29/786
CPC classification number: H01L21/268 , H01L21/428 , H01L29/6675 , H01L29/66757 , H01L29/66772 , H01L29/66969 , H01L29/78618 , H01L29/7869 , H01L29/78696 , H01L51/0027 , H01L51/105
Abstract: A method of manufacturing an electronic device comprises: providing a layer of semiconductor material comprising a first portion, a second portion, and a third portion, the third portion connecting the first portion to the second portion and providing a semiconductive channel for electrical current flow between the first and second portions; providing a gate terminal arranged with respect to said third portion such that a voltage may be applied to the gate terminal to control an electrical conductivity of said channel; and processing at least one of the first and second portions so as to have an electrical conductivity greater than an electrical conductivity of the channel when no voltage is applied to the gate terminal. In certain embodiments, the processing comprises exposing at least one of the first and second portions to electromagnetic radiation. The first and second portions may be laser annealed to increase their conductivities.
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公开(公告)号：US09978600B2
公开(公告)日：2018-05-22
申请号：US15369159
申请日：2016-12-05
Applicant: Pragmatic Printing Ltd.
Inventor： Richard Price , Catherine Ramsdale
IPC: H01L21/268 , H01L29/786 , H01L51/00 , H01L21/428 , H01L29/66 , H01L51/10
CPC classification number: H01L21/268 , H01L21/428 , H01L29/6675 , H01L29/66757 , H01L29/66772 , H01L29/66969 , H01L29/78618 , H01L29/7869 , H01L29/78696 , H01L51/0027 , H01L51/105
Abstract: A method of manufacturing an electronic device comprises: providing a layer of semiconductor material comprising a first portion, a second portion, and a third portion, the third portion connecting the first portion to the second portion and providing a semiconductive channel for electrical current flow between the first and second portions; providing a gate terminal arranged with respect to said third portion such that a voltage may be applied to the gate terminal to control an electrical conductivity of said channel; and processing at least one of the first and second portions so as to have an electrical conductivity greater than an electrical conductivity of the channel when no voltage is applied to the gate terminal. In certain embodiments, the processing comprises exposing at least one of the first and second portions to electromagnetic radiation. The first and second portions may be laser annealed to increase their conductivities.
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Patent Agency Ranking
公开(公告)号：US10204683B2
公开(公告)日：2019-02-12
申请号：US15303982
申请日：2015-04-14
Applicant: PRAGMATIC PRINTING LTD
Inventor： Richard Price , Catherine Ramsdale
Abstract: A method of manufacturing an electronic circuit comprises: providing an electronic circuit having a first configuration in which the circuit comprises a resistive element having a first resistance, and irradiating at least a part of the resistive element with electromagnetic radiation to change the resistance of the resistive element from the first resistance to a second resistance, the second resistance being lower than the first resistance. A method of storing data comprises: receiving a piece of data to be stored; determining a number according to the data; and irradiating at least part of a resistive element with that number of pulses of electromagnetic radiation to change a resistance of the resistive element from a first resistance to a second resistance, the second resistance being lower than the first resistance. A difference between the first resistance and the second resistance is dependent on the number. Corresponding circuits and data storage systems are disclosed.
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公开(公告)号：US20170040056A1
公开(公告)日：2017-02-09
申请号：US15303982
申请日：2015-04-14
Applicant: PRAGMATIC PRINTING LTD
Inventor： Richard Price , Catherine Ramsdale
IPC: G11C13/04
CPC classification number: G11C13/047 , G11B9/04 , G11B11/08 , G11B11/12 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/044
Abstract: A method of manufacturing an electronic circuit comprises: providing an electronic circuit having a first configuration in which the circuit comprises a resistive element having a first resistance, and irradiating at least a part of the resistive element with electromagnetic radiation to change the resistance of the resistive element from the first resistance to a second resistance, the second resistance being lower than the first resistance. A method of storing data comprises: receiving a piece of data to be stored; determining a number according to the data; and irradiating at least part of a resistive element with that number of pulses of electromagnetic radiation to change a resistance of the resistive element from a first resistance to a second resistance, the second resistance being lower than the first resistance. A difference between the first resistance and the second resistance is dependent on the number. Corresponding circuits and data storage systems are disclosed.
Abstract translation: 一种制造电子电路的方法包括：提供具有第一结构的电子电路，其中所述电路包括具有第一电阻的电阻元件，并且用电磁辐射照射所述电阻元件的至少一部分以改变所述电阻的电阻 元件从第一电阻到第二电阻，第二电阻低于第一电阻。 存储数据的方法包括：接收待存储的数据; 根据数据确定一个数字; 以及用所述数量的电磁辐射脉冲照射电阻元件的至少一部分，以将所述电阻元件的电阻从第一电阻改变为第二电阻，所述第二电阻低于所述第一电阻。 第一电阻和第二电阻之间的差异取决于数量。 公开了相应的电路和数据存储系统。
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公开(公告)号：US12136632B2
公开(公告)日：2024-11-05
申请号：US18231585
申请日：2023-08-08
Applicant: PRAGMATIC PRINTING LTD.
Inventor： Richard Price , Catherine Ramsdale , Brian Hardy Cobb , Feras Alkhalil
IPC: H01L27/12 , H01L21/02 , H01L21/027 , H01L21/285 , H01L21/306 , H01L21/3213 , H01L29/40 , H01L29/417
Abstract: A structure is disclosed, comprising: a first field effect transistor, FET, comprising a first source terminal, a first drain terminal, a first layer or body of semiconductive material arranged to provide a first semiconductive channel connecting the first source terminal to the first drain terminal, and a gate terminal arranged with respect to the first semiconductive channel such that a conductivity of the first semiconductive channel may be controlled by application of a voltage to the gate terminal; and a second FET comprising a second source terminal, a second drain terminal, a second layer or body of semiconductive material arranged to provide a second semiconductive channel connecting the second source terminal to the second drain terminal, and the gate terminal, the second conductive channel being arranged with respect to the gate terminal such that a conductivity of the second channel may be controlled by application of a voltage to the gate terminal. Methods of manufacturing such structures are also disclosed.
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公开(公告)号：US11978744B2
公开(公告)日：2024-05-07
申请号：US17315463
申请日：2021-05-10
Applicant: PRAGMATIC PRINTING LTD.
Inventor： Richard Price , Catherine Ramsdale , Brian Hardy Cobb , Feras Alkhalil
IPC: H01L27/12 , H01L21/02 , H01L21/027 , H01L21/285 , H01L21/306 , H01L21/3213 , H01L29/40 , H01L29/417
CPC classification number: H01L27/1251 , H01L21/02266 , H01L21/02631 , H01L21/0274 , H01L21/2855 , H01L21/30604 , H01L21/32133 , H01L27/1262 , H01L27/127 , H01L27/1288 , H01L29/401 , H01L29/41733
Abstract: A structure is disclosed, comprising: a first field effect transistor, FET, comprising a first source terminal, a first drain terminal, a first layer or body of semiconductive material arranged to provide a first semiconductive channel connecting the first source terminal to the first drain terminal, and a gate terminal arranged with respect to the first semiconductive channel such that a conductivity of the first semiconductive channel may be controlled by application of a voltage to the gate terminal; and a second FET comprising a second source terminal, a second drain terminal, a second layer or body of semiconductive material arranged to provide a second semiconductive channel connecting the second source terminal to the second drain terminal, and the gate terminal, the second conductive channel being arranged with respect to the gate terminal such that a conductivity of the second channel may be controlled by application of a voltage to the gate terminal. Methods of manufacturing such structures are also disclosed.
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公开(公告)号：US20160173099A1
公开(公告)日：2016-06-16
申请号：US14905737
申请日：2014-07-16
Applicant: PRAGMATIC PRINTING LTD
Inventor： Joao de Oliveira , Scott Darren White , Catherine Ramsdale
CPC classification number: H03K19/0944 , H03K3/0315 , H03K3/037 , H03K3/356017 , H03K17/16 , H03K19/09441 , H03K19/20 , H03K23/002
Abstract: An electronic circuit comprises: an input terminal; an output terminal; first and second supply rails; first, second, third, and fourth field effect transistors, FETs, each of a first type and each having respective gate, source and drain terminals; and first and second loads. The source of the first FET is connected to the first supply rail, the drain of the first FET and the source of the second FET are connected to the output terminal, the drain of the second FET is connected to the second supply rail, the gate of the third FET and the gate of the fourth FET are connected to the input terminal, the drain of the third FET is connected to the second supply rail, the first load is connected between the first supply rail and the source of the third FET, and the second load is connected between the drain of the fourth FET and the second supply rail. In one aspect of the invention, the gate of the first FET is connected to a node between the source of the third FET and the first load such that a voltage at the source of the third FET is applied to the gate of the first FET, and the gate of the second FET is connected to a node between the drain of the fourth FET and the second load such that a voltage at the drain of the fourth FET is applied to the gate of the second FET.
Abstract translation: 电子电路包括：输入端; 输出端子; 第一和第二供电轨; 第一，第二，第三和第四场效应晶体管，每个具有第一类型和每个具有相应的栅极，源极和漏极端子的FET; 以及第一和第二载荷。 第一FET的源极连接到第一电源轨，第一FET的漏极和第二FET的源极连接到输出端子，第二FET的漏极连接到第二电源轨，栅极 第三FET的栅极和第四FET的栅极连接到输入端子，第三FET的漏极连接到第二电源轨，第一负载连接在第一电源轨和第三FET的源极之间， 并且第二负载连接在第四FET的漏极和第二电源轨之间。 在本发明的一个方面，第一FET的栅极连接到第三FET的源极和第一负载之间的节点，使得第三FET的源极处的电压被施加到第一FET的栅极， 并且第二FET的栅极连接到第四FET的漏极和第二负载之间的节点，使得第四FET的漏极处的电压被施加到第二FET的栅极。
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