公开(公告)号：US20140138704A1

公开(公告)日：2014-05-22

申请号：US14165405

申请日：2014-01-27

申请人： Panasonic Corporation

发明人： Kenichiro TANAKA ,  Tetsuzo UEDA

IPC分类号： H01L29/778

CPC分类号： H01L29/778 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/66462 ,  H01L29/7787

摘要： A semiconductor device includes a field effect transistor that has a first nitride semiconductor layer and a second nitride semiconductor layer larger in bandgap than the first nitride semiconductor layer formed on a substrate in this order and a gate electrode, a source electrode, and a drain electrode, and uses two-dimensional electron gas formed at the interface between the first and second nitride semiconductor layers as the channel. The field effect transistor further has a p-type nitride semiconductor layer formed between the gate electrode and the drain electrode and electrically connected to the drain electrode.

摘要翻译： 半导体器件包括场效应晶体管，该场效应晶体管具有第一氮化物半导体层和具有比基板上形成的第一氮化物半导体层大的带隙的第二氮化物半导体层，栅电极，源电极和漏电极 并且使用形成在第一和第二氮化物半导体层之间的界面处的二维电子气体作为沟道。 场效应晶体管还具有形成在栅电极和漏电极之间并与漏电极电连接的p型氮化物半导体层。

公开(公告)号：US20130341682A1

公开(公告)日：2013-12-26

申请号：US13975085

申请日：2013-08-23

申请人： PANASONIC CORPORATION

发明人： Hidekazu UMEDA ,  Tetsuzo UEDA ,  Daisuke UEDA

IPC分类号： H01L29/06

CPC分类号： H01L29/0607 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/7786 ,  H01L29/861

摘要： A nitride semiconductor device includes a semiconductor substrate and a nitride semiconductor layer disposed on the semiconductor substrate. The semiconductor substrate includes a normal region, a carrier supplying region, and an interface current blocking region. The interface current blocking region surrounds the normal region and the carrier supplying region. The interface current blocking region and the carrier supplying region include impurities. The carrier supplying region has a conductivity type allowing the carrier supplying region to serve as a source of carriers supplied to or a destination of carriers supplied from a carrier layer generated at an interface between the nitride semiconductor layer and the semiconductor substrate. The interface current blocking region has a conductivity type allowing the interface current blocking region to serve as a potential barrier to the carriers.

摘要翻译： 氮化物半导体器件包括半导体衬底和设置在半导体衬底上的氮化物半导体层。 半导体衬底包括正常区域，载流子供应区域和界面电流阻挡区域。 界面电流阻挡区域围绕正常区域和载体供给区域。 界面电流阻挡区域和载流子供给区域包括杂质。 载体供给区域具有允许载流子供给区域用作从在氮化物半导体层和半导体基板之间的界面处产生的载流子层提供的载流子或目的地的载流子源的导电型。 界面电流阻挡区域具有允许界面电流阻挡区域用作载流子的势垒的导电类型。

公开(公告)号：US20140097433A1

公开(公告)日：2014-04-10

申请号：US14103155

申请日：2013-12-11

申请人： Panasonic Corporation

发明人： Noboru NEGORO ,  Hidekazu UMEDA ,  Nanako HIRASHITA ,  Tetsuzo UEDA

IPC分类号： H01L29/205 ,  H01L29/20 ,  H01L21/02 ,  H01L29/04

CPC分类号： H01L29/205 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/8258 ,  H01L27/0605 ,  H01L29/04 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/475 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786 ,  H01L29/872

摘要： A semiconductor device includes a substrate; a carrier traveling layer formed on the substrate, made of first group III nitride semiconductor, and containing carriers traveling in a direction along a principal surface of the substrate; a barrier layer formed on the carrier traveling layer and made of second group III nitride semiconductor having a wider band gap than the first group III nitride semiconductor; and an electrode formed on the barrier layer. The device further includes a cap layer formed on the barrier layer at a side of the electrode, and made of third group III nitride semiconductor containing a mixture of single crystals and polycrystals.

摘要翻译： 半导体器件包括衬底; 载体行进层，形成在所述基板上，由第一III族氮化物半导体构成，并且包含沿着所述基板的主表面的方向行进的载流子; 形成在所述载体行进层上并且由具有比所述第一III族氮化物半导体更宽的带隙的第二III族氮化物半导体制成的阻挡层; 以及形成在阻挡层上的电极。 该器件还包括形成在电极侧的阻挡层上的盖层，由包含单晶和多晶体的混合物的第三III族氮化物半导体制成。

公开(公告)号：US20140103459A1

公开(公告)日：2014-04-17

申请号：US14107758

申请日：2013-12-16

申请人： Panasonic Corporation

发明人： Yusuke KINOSHITA ,  Satoshi TAMURA ,  Yoshiharu ANDA ,  Tetsuzo UEDA

IPC分类号： H01L29/49 ,  H01L29/20 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/49 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66446 ,  H01L29/66462 ,  H01L29/66893 ,  H01L29/66924 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/808

摘要： A semiconductor device includes: a channel layer made of GaN; a barrier layer formed on the channel layer, the bather layer being made of AlGaN and having a larger band gap than the channel layer; a p-type GaN layer selectively formed on the barrier layer; a gate electrode made of ITO on the p-type GaN layer; and a source electrode and a drain electrode on regions of the barrier layer laterally outward of the gate electrode. The width of the gate electrode in the gate length direction is smaller than or equal to the width of the p-type GaN layer in the gate length direction, and the difference between the width of the gate electrode in the gate length direction and the width of the p-type GaN layer in the gate length direction is less than or equal to 0.2 μm.

摘要翻译： 半导体器件包括：由GaN制成的沟道层; 形成在沟道层上的阻挡层，所述泡沫层由AlGaN制成并且具有比沟道层更大的带隙; 选择性地形成在阻挡层上的p型GaN层; 在p型GaN层上由ITO制成的栅电极; 以及在栅电极的横向外侧的阻挡层的区域上的源电极和漏电极。 栅电极的栅极长度方向的宽度小于或等于栅极长度方向上p型GaN层的宽度，栅极长度方向的栅极宽度与宽度 在栅极长度方向上的p型GaN层的厚度小于或等于0.2μm。

公开(公告)号：US20130126943A1

公开(公告)日：2013-05-23

申请号：US13727354

申请日：2012-12-26

申请人： PANASONIC CORPORATION

发明人： Kenichiro TANAKA ,  Tetsuzo UEDA

IPC分类号： H01L29/778

CPC分类号： H01L29/7786 ,  H01L21/28575 ,  H01L29/0843 ,  H01L29/0891 ,  H01L29/2003 ,  H01L29/41766

摘要： An insulator is formed on the upper surface of a first semiconductor layer on at least a part of a portion above which a second semiconductor layer is not formed due to an opening. In the opening, a source electrode is formed to cover an insulator. The source electrode is formed to be in contact with an interface between the first semiconductor layer and the second semiconductor layer.

摘要翻译： 在第一半导体层的上表面上形成绝缘体的至少一部分上方，由于开口而不形成第二半导体层。 在开口中，形成源电极以覆盖绝缘体。 源电极形成为与第一半导体层和第二半导体层之间的界面接触。

公开(公告)号：US20130069115A1

公开(公告)日：2013-03-21

申请号：US13676740

申请日：2012-11-14

申请人： Panasonic Corporation

发明人： Satoshi NAKAZAWA ,  Tetsuzo UEDA ,  Yoshiharu ANDA ,  Naohiro TSURUMI ,  Ryo KAJITANI

IPC分类号： H01L29/78

CPC分类号： H01L29/78 ,  H01L29/0891 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41775 ,  H01L29/42316 ,  H01L29/475 ,  H01L29/66462 ,  H01L29/7787

摘要： A field effect transistor includes a nitride semiconductor multilayer structure formed on a substrate, a source electrode, a drain electrode, a gate electrode, an insulating film formed on the nitride semiconductor multilayer structure, and a field plate formed on and in contact with the insulating film, and having an end located between the gate electrode and the drain electrode. The insulating film includes a first film, and a second film having a dielectric breakdown voltage lower than that of the first film, and a thin film portion formed between the gate electrode and the drain electrode is formed in the insulating film. The field plate covers the thin film portion, and is connected to the source electrode in an opening.

摘要翻译： 场效应晶体管包括形成在衬底上的氮化物半导体多层结构，源电极，漏电极，栅电极，形成在氮化物半导体多层结构上的绝缘膜，以及形成在绝缘层上并与绝缘层形成接触的场板 并且具有位于栅电极和漏电极之间的端部。 绝缘膜包括第一膜和具有低于第一膜的介质击穿电压的第二膜，并且在绝缘膜中形成形成在栅电极和漏电极之间的薄膜部分。 场板覆盖薄膜部分，并且在开口中连接到源电极。

公开(公告)号：US20130043492A1

公开(公告)日：2013-02-21

申请号：US13658598

申请日：2012-10-23

申请人： Panasonic Corporation

发明人： Toshiyuki TAKIZAWA ,  Tetsuzo UEDA

IPC分类号： H01L29/778

CPC分类号： H01L29/66462 ,  H01L29/0843 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/7787

摘要： A nitride semiconductor transistor includes a heterojunction layer including a plurality of nitride semiconductor layers having different polarizations, and a gate electrode disposed on the heterojunction layer. An electron current reduction layer having a p-type conductivity is disposed between the heterojunction layer and the gate electrode to pass hole current therethrough and reduce electron current.

摘要翻译： 氮化物半导体晶体管包括具有不同极化的多个氮化物半导体层的异质结层和设置在异质结层上的栅电极。 在异质结层和栅电极之间设置具有p型导电性的电子电流降低层，以通过其中的空穴电流并减少电子电流。

公开(公告)号：US20170365698A1

公开(公告)日：2017-12-21

申请号：US15695904

申请日：2017-09-05

申请人： PANASONIC CORPORATION

发明人： Ryo KAJITANI ,  Daisuke SHIBATA ,  Kenichiro TANAKA ,  Masahiro ISHIDA ,  Tetsuzo UEDA

IPC分类号： H01L29/778 ,  H01L29/812 ,  H01L29/808

CPC分类号： H01L29/778 ,  H01L29/08 ,  H01L29/10 ,  H01L29/2003 ,  H01L29/72 ,  H01L29/808 ,  H01L29/812

摘要： A nitride semiconductor device includes: a substrate of a first conductivity type having a first surface and a second surface on a side of the substrate opposite the first surface; a first nitride semiconductor layer of the first conductivity type which is disposed on the first surface of the substrate and includes an acceptor impurity; a second nitride semiconductor layer of a second conductivity type disposed on the first nitride semiconductor layer, the second conductivity type being opposite to the first conductivity type; a first electrode disposed on the second surface of the substrate; a second electrode disposed on the first nitride semiconductor layer; and a gate electrode disposed on the second nitride semiconductor layer.

公开(公告)号：US20140231873A1

公开(公告)日：2014-08-21

申请号：US14265192

申请日：2014-04-29

申请人： PANASONIC CORPORATION

发明人： Daisuke SHIBATA ,  Masahiro HIKITA ,  Hidetoshi ISHIDA ,  Tetsuzo UEDA

IPC分类号： H01L29/778

CPC分类号： H01L29/7786 ,  H01L29/0619 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/7787 ,  H01L29/872

摘要： A nitride semiconductor device includes a semiconductor multilayer formed on a substrate, a first ohmic electrode and a Schottky electrode spaced apart from each other on the semicnductor multilayer; and a passivation film covering a top of the semiconductor multilayer. The semiconductor multilayer 102 includes a first nitride semiconductor layer, a second nitride semiconductor layer, and a p-type third nitride semiconductor layer 124 sequentially formed on the substrate. The third nitride semiconductor layer contains p-type impurities, and is selectively formed between the first ohmic electrode and the Schottky electrode in contact with the Schottky electrode.

摘要翻译： 氮化物半导体器件包括形成在衬底上的半导体层叠体，在半导体层上彼此分开的第一欧姆电极和肖特基电极; 以及覆盖半导体多层的顶部的钝化膜。 半导体层叠体102包括顺序形成在基板上的第一氮化物半导体层，第二氮化物半导体层和p型第三氮化物半导体层124。 第三氮化物半导体层含有p型杂质，并且选择性地形成在与肖特基电极接触的第一欧姆电极和肖特基电极之间。

公开(公告)号：US20140110759A1

公开(公告)日：2014-04-24

申请号：US14140325

申请日：2013-12-24

申请人： PANASONIC CORPORATION

发明人： Tomohiro MURATA ,  Daisuke SHIBATA ,  Tetsuzo UEDA

IPC分类号： H01L29/778 ,  H01L29/872

CPC分类号： H01L29/7783 ,  H01L27/0605 ,  H01L29/0619 ,  H01L29/0657 ,  H01L29/1029 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/7786 ,  H01L29/872

摘要： A semiconductor device includes a first hetero-junction body in which a first channel layer and a first barrier layer are bonded together; a second hetero-junction body in which a second channel layer formed on the first hetero-junction body and a second barrier layer are bonded together; a gate electrode in Schottky contact with the second barrier layer; and source and drain electrodes in ohmic contact with the first and second hetero-junction bodies. At least one of the first and second channel layers has such a thickness that an electron concentration in a 2DEG layer formed in the channel layer is not reduced.

摘要翻译： 半导体器件包括第一异质结体，其中第一沟道层和第一势垒层结合在一起; 第二异质结体，其中形成在第一异质结体上的第二沟道层和第二阻挡层结合在一起; 与第二阻挡层肖特基接触的栅电极; 以及与第一和第二异质结体欧姆接触的源极和漏极。 第一和第二沟道层中的至少一个具有这样的厚度，使得在沟道层中形成的2DEG层中的电子浓度不降低。