公开(公告)号：US20140077985A1

公开(公告)日：2014-03-20

申请号：US14116294

申请日：2013-02-21

Applicant: PANASONIC CORPORATION

Inventor： Yusuke Tokunaga

IPC: H03M3/00

CPC classification number: H03M3/32 ,  H03M3/02 ,  H03M3/39

Abstract: An analog-to-digital conversion circuit includes: a clock generating circuit which generates a clock signal including a first initial period and plural normal periods following the first initial period, the first initial period being one of a high period and a low period and being a first period immediately after a reset release, each of the normal periods being one of a high period and a low period and shorter than the first initial period; and an incremental analog-to-digital converter which operates using the clock signal.

Abstract translation: 一种模拟 - 数字转换电路包括：时钟发生电路，其产生包括第一初始周期和第一初始周期之后的多个正常周期的时钟信号，第一初始周期是高周期和低周期之一，并且是 紧接着复位释放之后的第一时段，每个正常周期是高周期和低周期之一，并且短于第一初始周期; 以及使用时钟信号进行操作的增量型模 - 数转换器。

公开(公告)号：US08912941B2

公开(公告)日：2014-12-16

申请号：US14116294

申请日：2013-02-21

Applicant: Panasonic Corporation

Inventor： Yusuke Tokunaga

IPC: H03M1/12 ,  H03M3/02 ,  H03M3/00

CPC classification number: H03M3/32 ,  H03M3/02 ,  H03M3/39

Abstract: An analog-to-digital conversion circuit includes: a clock generating circuit which generates a clock signal including a first initial period and plural normal periods following the first initial period, the first initial period being one of a high period and a low period and being a first period immediately after a reset release, each of the normal periods being one of a high period and a low period and shorter than the first initial period; and an incremental analog-to-digital converter which operates using the clock signal.

Abstract translation: 一种模拟 - 数字转换电路包括：时钟发生电路，其产生包括第一初始周期和第一初始周期之后的多个正常周期的时钟信号，第一初始周期是高周期和低周期之一，并且是 紧接着复位释放之后的第一时段，每个正常周期是高周期和低周期之一，并且短于第一初始周期; 以及使用时钟信号进行操作的增量型模 - 数转换器。

公开(公告)号：US20150255173A1

公开(公告)日：2015-09-10

申请号：US14431501

申请日：2013-09-27

Applicant: PANASONIC CORPORATION

Inventor： Yusuke Tokunaga

IPC: G11C27/02 ,  H03M1/12

CPC classification number: G11C27/026 ,  H03F3/005 ,  H03F3/45475 ,  H03F2203/45514 ,  H03F2203/45551 ,  H03F2203/45634 ,  H03H19/004 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1255 ,  H03M1/804

Abstract: A switched capacitor circuit according to the present invention includes: a capacitor including a first terminal to which the input voltage is applied and a second terminal; a capacitor including a third terminal and a fourth terminal; an inverting amplifier including a second output terminal and a second input terminal which is connected to the fourth terminal; a capacitor including a fifth terminal and a sixth terminal; a capacitor including a seventh terminal and an eighth terminal and included in an electrical path between the second output terminal and the fifth terminal; and a capacitor including a ninth terminal and a tenth terminal connected to the second terminal and the sixth terminal, respectively. The third terminal is connected to the second terminal. The sixth terminal is connected to the output terminal.

Abstract translation: 根据本发明的开关电容器电路包括：电容器，包括施加有输入电压的第一端子和第二端子; 包括第三端子和第四端子的电容器; 反相放大器，包括连接到第四端子的第二输出端子和第二输入端子; 包括第五端子和第六端子的电容器; 电容器，包括第七端子和第八端子，并且包括在所述第二输出端子和所述第五端子之间的电气路径中; 以及包括分别连接到第二端子和第六端子的第九端子和第十端子的电容器。 第三终端连接到第二终端。 第六个端子连接到输出端子。

公开(公告)号：US08508269B2

公开(公告)日：2013-08-13

申请号：US13724803

申请日：2012-12-21

Applicant: Panasonic Corporation

Inventor： Yusuke Tokunaga ,  Shiro Sakiyama

IPC: H03L7/06

CPC classification number: H03L7/00 ,  H03K4/501

Abstract: An oscillator circuit complementarily increases or reduces, in response to a transition of a signal level of a reference clock, a signal level of a first oscillation signal and a signal level of a second oscillation signal. An oscillation control circuit compares the first and second oscillation signals to a comparison voltage, and transitions the signal level of the reference clock in accordance with a result of the comparison. A reference control circuit increases or reduces the comparison voltage so that a difference between a signal level of an intermediate signal which is proportional to respective swings of the first and second oscillation signals and a reference voltage is reduced. A reference voltage control circuit increases or reduces the reference voltage according to a frequency difference between a basis clock and the reference clock.

Abstract translation: 响应于参考时钟的信号电平，第一振荡信号的信号电平和第二振荡信号的信号电平的转变，振荡器电路互补地增加或减小。 振荡控制电路将第一和第二振荡信号与比较电压进行比较，并根据比较结果转换参考时钟的信号电平。 参考控制电路增加或减小比较电压，使得与第一和第二振荡信号的相应摆动成比例的中间信号的信号电平与参考电压之间的差减小。 参考电压控制电路根据基准时钟和参考时钟之间的频率差增加或减小参考电压。

公开(公告)号：US09491385B2

公开(公告)日：2016-11-08

申请号：US14749951

申请日：2015-06-25

Applicant: Panasonic Corporation

Inventor： Yusuke Tokunaga

IPC: H04N3/14 ,  H04N5/335 ,  H04N5/374 ,  G06G7/186 ,  H03H19/00 ,  G01K1/00 ,  H03K3/356 ,  H03M1/12 ,  H03K19/0185 ,  H04N5/378

CPC classification number: H04N5/374 ,  G01K1/00 ,  G06G7/186 ,  H03H19/004 ,  H03K3/356104 ,  H03K19/018521 ,  H03M1/1245 ,  H04N5/378

Abstract: A switched capacitor circuit includes: a capacitor including a first terminal to which the input voltage is applied and a second terminal; an inverting amplifier including a second input terminal connected to the second terminal; a capacitor including a third terminal, a fourth terminal, and a fifth terminal which is connected to an output terminal; a capacitor including a seventh terminal, a sixth terminal connected to the second output terminal, and an eighth terminal connected to the third terminal; a capacitor connected in series between the second terminal and the output terminal; and an offset compensation unit which outputs an offset voltage having a value of a short-circuit voltage of the inverting amplifier to the fourth terminal and the seventh terminal.

Abstract translation: 开关电容电路包括：电容器，包括施加有输入电压的第一端子和第二端子; 反相放大器，包括连接到第二端子的第二输入端子; 电容器，包括连接到输出端子的第三端子，第四端子和第五端子; 电容器，包括第七端子，连接到第二输出端子的第六端子和连接到第三端子的第八端子; 在第二端子和输出端子之间串联连接的电容器; 以及偏移补偿单元，其向第四端子和第七端子输出具有反相放大器的短路电压值的偏移电压。