公开(公告)号：US20220181209A1

公开(公告)日：2022-06-09

申请号：US17456914

申请日：2021-11-30

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi HARIKAI ,  Shogo OKITA ,  Akihiro ITOU ,  Toshiyuki TAKASAKI

IPC: H01L21/78 ,  H01L21/3065 ,  H01L21/304

Abstract: The element chip manufacturing method includes: a preparing process of preparing a substrate 1 including a plurality of element regions EA and a dividing region DA, the substrate 1 having a first principal surface 1X and a second principal surface 1Y; a groove forming process of forming a groove 13 in the dividing region DA from the first principal surface 1X side; and a grinding process of grinding the substrate 1 from the second principal surface 1Y side, to divide the substrate 1 into a plurality of element chips 20. The groove 13 includes a first region 13a constituted by a side surface having a first surface roughness, and a second region 13b constituted by a side surface having a second surface roughness larger than the first surface roughness. In the grinding process, grinding of the substrate 1 is performed until reaching the first region 13a of the groove 13.

公开(公告)号：US20210287913A1

公开(公告)日：2021-09-16

申请号：US17188005

申请日：2021-03-01

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo OKITA ,  Atsushi HARIKAI ,  Akihiro ITOU

IPC: H01L21/311 ,  H01L21/78 ,  H01L21/683

Abstract: An etching method including: a preparation step of preparing a resin layer and an electronic component supported thereby; and a resin etching step of etching the resin layer. The electronic component has a first surface covered with a protective film, a second surface opposite thereto, and a sidewall therebetween. The second surface is facing the resin layer. The resin layer is larger than the electronic component when seen from the first surface side. The resin etching step includes: a deposition step of depositing a first film, using a first plasma, on a surface of the protective film and a surface of the resin layer; and a removal step of removing, using a second plasma, the first film deposited on the resin layer and at least part of the resin layer. The deposition and removal steps are alternately repeated, with the protective film allowed to continue to exist.

公开(公告)号：US20190304838A1

公开(公告)日：2019-10-03

申请号：US16362933

申请日：2019-03-25

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidefumi SAEKI ,  Atsushi HARIKAI ,  Shogo OKITA

IPC: H01L21/78 ,  H01L23/544 ,  H01L21/268 ,  H01L21/3065 ,  B23K26/00 ,  B23K26/364

Abstract: A manufacturing process of an element chip comprises a preparing step for preparing a substrate having first and second sides opposed to each other, the substrate containing a semiconductor layer, a wiring layer and a resin layer formed on the first side, and the substrate including a plurality of dicing regions and element regions defined by the dicing regions. Also, the manufacturing process comprises a laser grooving step for irradiating a laser beam onto the dicing regions to form grooves so as to expose the semiconductor layer along the dicing regions. Further, the manufacturing process comprises a dicing step for plasma-etching the semiconductor layer along the dicing regions through the second side to divide the substrate into a plurality of the element chips. The laser grooving step includes a melting step for melting a surface of the semiconductor layer exposed along the dicing regions.

公开(公告)号：US20170069522A1

公开(公告)日：2017-03-09

申请号：US15252899

申请日：2016-08-31

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Mitsuru HIROSHIMA ,  Atsushi HARIKAI

IPC: H01L21/683 ,  H01L21/78 ,  H01L21/304

CPC classification number: H01L21/6836 ,  H01L21/304 ,  H01L21/3081 ,  H01L21/6835 ,  H01L21/78 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834

Abstract: In a method of fabricating element chips, a method of forming a mask pattern, and a method of processing a substrate, a process sequence is set such that developing in which the exposure-ended protection film is patterned is performed, after grinding in which the substrate is thinned by grinding a second surface opposite to a first surface to which a photosensitive protection film is pasted. Thereby, it is possible to perform the grinding for thinning in a state where the protection film is stable without being patterned, and to prevent the substrate or the protection film on which a mask pattern of the substrate is formed from being damaged at the time of the grinding, even in a case where a thin substrate of a wafer shape becomes a target.

Abstract translation: 在制造元件芯片的方法中，形成掩模图案的方法和处理基板的方法，设置处理顺序，使得进行曝光结束保护膜的图案化的显影，在其中 通过研磨与粘贴有光敏保护膜的第一表面相对的第二表面来使基板变薄。 由此，可以在图案化保护膜稳定的状态下进行用于减薄的研磨，并且可以防止在基板或保护膜上形成有基板的掩模图案的基板或保护膜在 即使在晶片形状的薄基板成为目标的情况下也可进行研磨。

公开(公告)号：US20190198396A1

公开(公告)日：2019-06-27

申请号：US16218554

申请日：2018-12-13

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidefumi SAEKI ,  Atsushi HARIKAI

IPC: H01L21/78 ,  H01L21/3065 ,  H01L21/304 ,  H01L21/268 ,  H01L21/311

Abstract: A manufacturing process of an element chip, comprising a substrate preparing step for preparing a substrate having first and second sides opposed to each other, and including a plurality of dicing regions and element regions defined by the dicing regions, the first side being covered by a protective film, a first laser-grooving step for forming a plurality of grooves by irradiating a laser beam to the first side along the dicing regions, and a plasma-dicing step for plasma-etching the substrate along the grooves in depth through a plasma exposure, thereby to dice the substrate into a plurality of element chips, wherein the second side of the substrate and an annular frame are held on a holding sheet in the substrate preparing step, and wherein the laser beam is irradiated only in a region inside an outer edge of the substrate in the first laser-grooving step.

公开(公告)号：US20190122892A1

公开(公告)日：2019-04-25

申请号：US16154930

申请日：2018-10-09

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo OKITA ,  Atsushi HARIKAI ,  Akihiro ITOU ,  Noriyuki MATSUBARA

IPC: H01L21/3065 ,  H01L21/67 ,  H01L21/683 ,  H01L21/687 ,  H01L21/311 ,  H01L21/677

Abstract: Provided is a plasma processing method which comprises steps of preparing a conveying carrier including a holding sheet and a frame provided on a peripheral region of the holding sheet, adhering the substrate on the holding sheet in an inner region inside the peripheral region to hold the substrate on the conveying carrier, sagging the holding sheet in the inner region, setting the conveying carrier on a stage provided within a plasma processing apparatus to contact the holding sheet on the stage so that the holding sheet in the inner region touches the stage before the holding sheet in the peripheral region does, and plasma processing the substrate.

公开(公告)号：US20180174908A1

公开(公告)日：2018-06-21

申请号：US15811733

申请日：2017-11-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidehiko KARASAKI ,  Hidefumi SAEKI ,  Atsushi HARIKAI

IPC: H01L21/78 ,  H01L21/268

CPC classification number: H01L21/78 ,  B23K26/0622 ,  B23K26/364 ,  B23K26/402 ,  B23K2101/40 ,  B23K2103/172 ,  B23K2103/56 ,  H01J37/32 ,  H01L21/2686 ,  H01L21/30655

Abstract: A manufacturing process of an element chip comprises a preparation step for preparing a substrate, the substrate including first and second streets crossing each other to define a plurality of element regions. Also, it comprises a first shallow-groove formation step for radiating a laser beam along the first streets to form a plurality of first shallow grooves being shallower than a thickness of the substrate, a second shallow-groove formation step for radiating the laser beam along the second streets to form a plurality of second shallow grooves being shallower than a thickness of the substrate, a first groove formation step for radiating the laser beam along the first shallow grooves to form a plurality of first grooves, and a plasma dicing step for etching the substrate along the first grooves and the second shallow grooves by a plasma exposure to dice the substrate into a plurality of element chips.

公开(公告)号：US20230114557A1

公开(公告)日：2023-04-13

申请号：US17937512

申请日：2022-10-03

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi HARIKAI ,  Shogo OKITA

IPC: H01J37/32

Abstract: A plasma processing apparatus including: a chamber; a plasma generation unit configured to generate a plasma in the chamber; a stage 111 for placing a conveying carrier 10, the stage provided in the chamber; a cover 124 for covering at least part of the conveying carrier placed on the stage; a relative position change unit capable of changing a relative distance between the cover 124 and the stage 111 to a first distance and to a second distance smaller than the first distance; a determination unit configured to determine a placed state of the conveying carrier 10; and a control unit. The determination unit determines the placed state of the conveying carrier while the distance between the cover 124 and the stage 111 is the first distance, and the plasma processing is performed while the distance between the cover 124 and the stage 111 is the second distance.

公开(公告)号：US20210057227A1

公开(公告)日：2021-02-25

申请号：US16993466

申请日：2020-08-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Akihiro ITOU ,  Atsushi HARIKAI ,  Toshiyuki TAKASAKI ,  Shogo OKITA

IPC: H01L21/3065 ,  H01L21/02

Abstract: An element chip smoothing method including: an element chip preparation step of preparing at least one element chip including a first surface covered with a resin film, a second surface opposite the first surface, and a sidewall connecting the first surface to the second surface and having ruggedness; a sidewall cleaning step of exposing the element chip to a first plasma, to remove deposits adhering to the sidewall, with the resin film allowed to continue to exist; a sidewall oxidation step of exposing the element chip to a second plasma, after the sidewall cleaning step, to oxidize a surface of the sidewall, with the resin film allowed to continue to exist; and a sidewall etching step of exposing the element chip to a third plasma, after the sidewall oxidation step, to etch the sidewall, with the resin film allowed to continue to exist.

公开(公告)号：US20200381304A1

公开(公告)日：2020-12-03

申请号：US16881165

申请日：2020-05-22

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidefumi SAEKI ,  Hidehiko KARASAKI ,  Shogo OKITA ,  Atsushi HARIKAI ,  Akihiro ITOU

IPC: H01L21/82 ,  H01L21/56 ,  H01L21/311 ,  H01L21/3065

Abstract: An element chip manufacturing method including: attaching a substrate via a die attach film (DAF) to a holding sheet; forming a protective film that covers the substrate; forming an opening in the protective film with a laser beam, to expose the substrate in the dicing region therefrom; exposing the substrate to a first plasma to etch the substrate exposed from the opening, so that a plurality of element chips are formed from the substrate and so that the DAF is exposed from the opening; exposing the substrate to a second plasma to etch the die attach film exposed from the opening, so that the DAF is split so as to correspond to the element chips; and detaching the element chips from the holding sheet, together with the split DAF. The DAF is larger than the substrate. The method includes irradiating the laser beam to the DAF protruding from the substrate.