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公开(公告)号：US20240162091A1
公开(公告)日：2024-05-16
申请号：US18501124
申请日：2023-11-03
Inventor： Hidehiko KARASAKI , Shogo OKITA , Toshiyuki TAKASAKI , Ryota FURUKAWA
IPC: H01L21/78 , H01L21/308
CPC classification number: H01L21/78 , H01L21/3086 , H01L21/3065
Abstract: The disclosed element chip manufacturing method includes: a first step of imparting hydrophilicity to a first surface 11 of a substrate 1, the first surface 11 including element regions 11A and dicing regions 11B defining the element regions 11A; a second step of applying a raw material liquid containing a water-soluble resin onto the first surface 11, to form a water-soluble resin layer 20 on the first surface 11; a third step of applying a laser beam to the water-soluble resin layer 20 covering the dicing regions 11B, to form openings 20a that expose the dicing regions 11B, in the water-soluble resin layer 20; a fourth step of etching the dicing regions 11B exposed at the openings 20a, with plasma, to obtain element chips 30; and a fifth step of removing the water-soluble resin layer 20 by bringing the element chips 30 into contact with a water-containing cleaning liquid.
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公开(公告)号：US20220181209A1
公开(公告)日：2022-06-09
申请号：US17456914
申请日：2021-11-30
Inventor： Atsushi HARIKAI , Shogo OKITA , Akihiro ITOU , Toshiyuki TAKASAKI
IPC: H01L21/78 , H01L21/3065 , H01L21/304
Abstract: The element chip manufacturing method includes: a preparing process of preparing a substrate 1 including a plurality of element regions EA and a dividing region DA, the substrate 1 having a first principal surface 1X and a second principal surface 1Y; a groove forming process of forming a groove 13 in the dividing region DA from the first principal surface 1X side; and a grinding process of grinding the substrate 1 from the second principal surface 1Y side, to divide the substrate 1 into a plurality of element chips 20. The groove 13 includes a first region 13a constituted by a side surface having a first surface roughness, and a second region 13b constituted by a side surface having a second surface roughness larger than the first surface roughness. In the grinding process, grinding of the substrate 1 is performed until reaching the first region 13a of the groove 13.
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公开(公告)号：US20240312841A1
公开(公告)日：2024-09-19
申请号：US18602117
申请日：2024-03-12
Inventor： Hidefumi SAEKI , Hidehiko KARASAKI , Shogo OKITA , Toshiyuki TAKASAKI , Akihiro ITOU
IPC: H01L21/78 , B23K26/36 , H01L21/56 , H01L21/683
CPC classification number: H01L21/78 , B23K26/36 , H01L21/561 , H01L21/568 , H01L21/6836 , H01L2221/68327
Abstract: An element chip manufacturing method disclosed herein includes a preparation process of preparing a substrate having a semiconductor layer, a wiring layer, a plurality of element areas and a dividing area, a resin layer formation process of forming a resin layer covering the wiring layer, an opening formation process of irradiating the wiring layer and the resin layer in the dividing area to form an opening in which the semiconductor layer is exposed in the dividing area, a reflow process of reducing the opening by reflowing the resin layer, and a singulation process of dividing the substrate into a plurality of element chips each including a different one of the element areas, by performing etching of the substrate with plasma along the opening reduced in the reflow process, using the resin layer as a mask.
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公开(公告)号：US20210057227A1
公开(公告)日：2021-02-25
申请号：US16993466
申请日：2020-08-14
Inventor： Akihiro ITOU , Atsushi HARIKAI , Toshiyuki TAKASAKI , Shogo OKITA
IPC: H01L21/3065 , H01L21/02
Abstract: An element chip smoothing method including: an element chip preparation step of preparing at least one element chip including a first surface covered with a resin film, a second surface opposite the first surface, and a sidewall connecting the first surface to the second surface and having ruggedness; a sidewall cleaning step of exposing the element chip to a first plasma, to remove deposits adhering to the sidewall, with the resin film allowed to continue to exist; a sidewall oxidation step of exposing the element chip to a second plasma, after the sidewall cleaning step, to oxidize a surface of the sidewall, with the resin film allowed to continue to exist; and a sidewall etching step of exposing the element chip to a third plasma, after the sidewall oxidation step, to etch the sidewall, with the resin film allowed to continue to exist.
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公开(公告)号：US20240266201A1
公开(公告)日：2024-08-08
申请号：US18432232
申请日：2024-02-05
Inventor： Toshiyuki TAKASAKI , Shogo OKITA , Minghui ZHAO
IPC: H01L21/683 , H01J37/32
CPC classification number: H01L21/6833 , H01J37/32715 , H01J37/3299 , H01J2237/24564 , H01J2237/24585 , H01J2237/332 , H01J2237/334
Abstract: A plasma processing apparatus includes an ESC system having an ESC electrode, a plasma generator generating a first and a second plasma, a controller controlling the ESC system and the plasma generator such that a first or second processing with the first or second processing is performed on a substrate chucked to a stage, and an abnormality detector detecting abnormality, based on a plurality of parameters. The abnormality detector performs an abnormality detection during predetermined period DT immediately after switching between the first processing and the second processing, based on a first parameter including a monitoring information related to voltage V and/or current I applied to the ESC electrode and does not include a monitoring information related to pressure PR within a chamber, and performs an abnormality detection during other than predetermined period DT, based on a second parameter including the monitoring information related to pressure PR within the chamber.
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Patent Agency Ranking
公开(公告)号：US20220199411A1
公开(公告)日：2022-06-23
申请号：US17550309
申请日：2021-12-14
Inventor： Toshiyuki TAKASAKI , Ryota FURUKAWA , Atsushi HARIKAI , Shogo OKITA
IPC: H01L21/3065 , H01L21/78 , H01L21/311
Abstract: Disclosed is a method for producing element chips. The method includes: a preparing step of preparing a substrate 10 that is held on a holding sheet 22 that is supported by a frame 21, the substrate including element regions and dicing regions; a protective film forming step of forming a protective film 15 so as to cover the frame 21, the holding sheet 22, and the substrate 10; a patterning step of removing a part of the protective film 15 so as to expose the dicing regions of the substrate 10; a plasma dicing step including a process that uses a plasma that contains fluorine, the plasma dicing step being a step of individualizing the substrate 10 into a plurality of element chips; and a fluorine removing step of removing, together with the protective film 15, fluorine attached to the protective film 15 in the plasma dicing step.
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公开(公告)号：US20250022682A1
公开(公告)日：2025-01-16
申请号：US18766729
申请日：2024-07-09
Inventor： Shogo OKITA , Takahiro MIYAI , Yoshiyuki WADA , Naoaki TAKEDA , Toshiyuki TAKASAKI , Hisao NAGAI , Seiya NAGANO
IPC: H01J37/32
Abstract: A plasma generation unit includes: a first coil that includes first conductors that are connected in parallel to each other; and a first distribution portion that distributes, to each of the first conductors, first high frequency power to be supplied to the first coil. The first distribution portion includes: a first input portion to which the first high frequency power is input; a first branch portion at which the first high frequency power input to the first input portion is divided and delivered into first branch lines; and second branch portions at each of which a corresponding one of the first branch lines branches out into second branch lines. Each of the second branch lines is connected to one of first application portions that are included in the first conductors. The first branch lines have a substantially equal length. The second branch lines have a substantially equal length.
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公开(公告)号：US20250014877A1
公开(公告)日：2025-01-09
申请号：US18761458
申请日：2024-07-02
Inventor： Hisao NAGAI , Shogo OKITA , Toshiyuki TAKASAKI , Seiya NAGANO , Naoaki TAKEDA , Takahiro MIYAI
IPC: H01J37/32
Abstract: A plasma processing apparatus including a chamber, a placement unit which is disposed in the chamber and on which a substrate is to be placed, a plasma generation unit configured to generate a plasma within the chamber, a gas supply unit configured to supply a raw material gas of the plasma into the chamber, a measurement unit configured to measure and output a distribution information regarding a plasma distribution in the chamber, a control unit configured to control the plasma generation unit and the gas supply unit so as to repeat a unit processing on the substrate, a memory unit configured to store process conditions including conditions for the unit processing, and a modification unit configured to modify the process conditions. The measurement unit measures the distribution information (N) in the unit processing (N) at an Nth time, where N is an integer. When the distribution information (N) satisfies a predetermined condition, the modification unit modifies the process conditions in the unit processing (M) at an Mth time, where M is any integer equal to or greater than (N+1).
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公开(公告)号：US20230170186A1
公开(公告)日：2023-06-01
申请号：US18056294
申请日：2022-11-17
Inventor： Shogo OKITA , Yoshiyuki WADA , Takahiro MIYAI , Naoaki TAKEDA , Toshihiro WADA , Toshiyuki TAKASAKI
IPC: H01J37/32
CPC classification number: H01J37/32266 , H01J37/32449 , H01J2237/141
Abstract: Disclosed is a plasma processing apparatus 10 including a chamber 11, a stage 12, a dielectric member 13, a cover 14, a gas introduction path 15, and an induction coil 16. The induction coil 16 includes a first induction coil 17 installed so as to overlap a central region R1 of the dielectric member 13, and a second induction coil 18 installed so as to overlap a peripheral region R2 outside the central region R1 of the dielectric member 13. The cover 14 has a first gas hole 14c formed at a position overlapping the central region R1 and a second gas hole 14d formed at a position overlapping the peripheral region R2. The gas introduction path 15 has a first gas introduction path 15a communicating with the first gas hole 14c and a second gas introduction path 15b communicating with the second gas hole 14d.
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公开(公告)号：US20220165577A1
公开(公告)日：2022-05-26
申请号：US17455678
申请日：2021-11-19
Inventor： Toshiyuki TAKASAKI , Shogo OKITA , Akihiro ITOU , Atsushi HARIKAI
IPC: H01L21/3065 , H01L21/78
Abstract: A plasma processing method including: exposing to a first plasma a substrate having a compound semiconductor layer and a mask partially covering a surface of the compound semiconductor layer, to form a protective film at least on the bottom of a groove formed in a region where the compound semiconductor layer is not covered with the mask; removing the protective film at the bottom by exposing the substrate to a second plasma, to expose the compound semiconductor layer; and removing the conductive semiconductor layer exposed at the bottom of the groove by exposing the substrate to a third plasma generated from a gas containing chlorine and/or bromine, while allowing a reaction product between the compound semiconductor layer and the third plasma to accumulate on an upper portion of the groove. The reaction product is removed by applying a high-frequency power to a stage on which the substrate is placed.
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