公开(公告)号：US20240413013A1

公开(公告)日：2024-12-12

申请号：US18588505

申请日：2024-02-27

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo OKITA

IPC: H01L21/78 ,  H01L23/00

Abstract: The method includes a process of preparing a substrate 1 that includes a first layer 2 and a second layer 3 and includes a division region, a process of flattening an upper surface of the layer 3, a process of forming a protective layer 4 on the flattened upper surface to form a boundary 6 between the layer 3 and the layer 4, a process of removing the layers 3, 4 in the division region using laser light to form a groove 5 reaching the layer 2, and depositing, on side walls of the groove 5, a deposit D so as to cover the boundary 6, a process of removing the deposit D to expose the boundary 6 on the side walls, and a process of etching the layer 2 by exposing the groove 5 to plasma, and thereby dividing the substrate 1 into a plurality of element chips.

公开(公告)号：US20220367273A1

公开(公告)日：2022-11-17

申请号：US17661584

申请日：2022-05-02

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidehiko KARASAKI ,  Shogo OKITA

IPC: H01L21/78 ,  H01L23/544

Abstract: A method including: a step of preparing a substrate that includes a first layer having a dicing region and a mark, and including a semiconductor layer, and a second layer including a metal film; a step of removing the metal film, to expose the semiconductor layer corresponding to a first region that corresponds to the mark; a step of smoothing a surface of the exposed semiconductor layer; a step of imaging the substrate, with a camera sensing predetermined electromagnetic waves, to detect a position of the mark through the semiconductor layer, and calculating a second region corresponding to the dicing region; and a step of removing the metal film, to expose the semiconductor layer corresponding to the second region. In the smoothing step, the surface of the semiconductor layer is smoothed so as to have a surface roughness of 1/4 or less of a wavelength of the predetermined electromagnetic waves.

公开(公告)号：US20190122892A1

公开(公告)日：2019-04-25

申请号：US16154930

申请日：2018-10-09

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo OKITA ,  Atsushi HARIKAI ,  Akihiro ITOU ,  Noriyuki MATSUBARA

IPC: H01L21/3065 ,  H01L21/67 ,  H01L21/683 ,  H01L21/687 ,  H01L21/311 ,  H01L21/677

Abstract: Provided is a plasma processing method which comprises steps of preparing a conveying carrier including a holding sheet and a frame provided on a peripheral region of the holding sheet, adhering the substrate on the holding sheet in an inner region inside the peripheral region to hold the substrate on the conveying carrier, sagging the holding sheet in the inner region, setting the conveying carrier on a stage provided within a plasma processing apparatus to contact the holding sheet on the stage so that the holding sheet in the inner region touches the stage before the holding sheet in the peripheral region does, and plasma processing the substrate.

公开(公告)号：US20170178871A1

公开(公告)日：2017-06-22

申请号：US15444775

申请日：2017-02-28

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo OKITA

IPC: H01J37/32 ,  H01L21/683 ,  H01L21/3065 ,  H01L21/67

CPC classification number: H01J37/32697 ,  H01J37/3211 ,  H01J37/3244 ,  H01J37/32568 ,  H01J37/32715 ,  H01J37/32724 ,  H01J37/32816 ,  H01J2237/002 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/67069 ,  H01L21/6831 ,  H01L21/6833 ,  H01L21/78

Abstract: A dry etching apparatus plasma processes a wafer held by a carrier having a frame and an holding sheet. The carrier is placed on an electrode unit of a stage provided in a chamber. The electrode unit is cooled by a cooling section configured to cool the electrode unit. An upper face of the electrode unit is at least as large as the back side of the carrier. The holding sheet and the frame are cooled effectively by the heat transfer to the stage.

公开(公告)号：US20240162091A1

公开(公告)日：2024-05-16

申请号：US18501124

申请日：2023-11-03

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidehiko KARASAKI ,  Shogo OKITA ,  Toshiyuki TAKASAKI ,  Ryota FURUKAWA

IPC: H01L21/78 ,  H01L21/308

CPC classification number: H01L21/78 ,  H01L21/3086 ,  H01L21/3065

Abstract: The disclosed element chip manufacturing method includes: a first step of imparting hydrophilicity to a first surface 11 of a substrate 1, the first surface 11 including element regions 11A and dicing regions 11B defining the element regions 11A; a second step of applying a raw material liquid containing a water-soluble resin onto the first surface 11, to form a water-soluble resin layer 20 on the first surface 11; a third step of applying a laser beam to the water-soluble resin layer 20 covering the dicing regions 11B, to form openings 20a that expose the dicing regions 11B, in the water-soluble resin layer 20; a fourth step of etching the dicing regions 11B exposed at the openings 20a, with plasma, to obtain element chips 30; and a fifth step of removing the water-soluble resin layer 20 by bringing the element chips 30 into contact with a water-containing cleaning liquid.

公开(公告)号：US20220384177A1

公开(公告)日：2022-12-01

申请号：US17663452

申请日：2022-05-16

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidehiko KARASAKI ,  Shogo OKITA

IPC: H01L21/02 ,  H01L21/68 ,  H01L21/463

Abstract: A method including: a step of preparing a substrate that includes a first layer having a first principal surface provided with a dicing region, and a mark, and a second principal surface, and includes a semiconductor layer; a step of covering a first region corresponding to the mark on the second principal surface, with a resist film; a step of forming a metal film on the second principal surface; a step of removing the resist film, to expose the semiconductor layer corresponding to the first region; a step of imaging the substrate, with a camera, to detect a position of the mark through the semiconductor layer, and calculating a second region corresponding to the dicing region on a surface of the metal film; and a step of irradiating a laser beam to the second region, to remove the metal film and expose the semiconductor layer corresponding to the second region.

公开(公告)号：US20220181209A1

公开(公告)日：2022-06-09

申请号：US17456914

申请日：2021-11-30

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi HARIKAI ,  Shogo OKITA ,  Akihiro ITOU ,  Toshiyuki TAKASAKI

IPC: H01L21/78 ,  H01L21/3065 ,  H01L21/304

Abstract: The element chip manufacturing method includes: a preparing process of preparing a substrate 1 including a plurality of element regions EA and a dividing region DA, the substrate 1 having a first principal surface 1X and a second principal surface 1Y; a groove forming process of forming a groove 13 in the dividing region DA from the first principal surface 1X side; and a grinding process of grinding the substrate 1 from the second principal surface 1Y side, to divide the substrate 1 into a plurality of element chips 20. The groove 13 includes a first region 13a constituted by a side surface having a first surface roughness, and a second region 13b constituted by a side surface having a second surface roughness larger than the first surface roughness. In the grinding process, grinding of the substrate 1 is performed until reaching the first region 13a of the groove 13.

公开(公告)号：US20210287913A1

公开(公告)日：2021-09-16

申请号：US17188005

申请日：2021-03-01

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo OKITA ,  Atsushi HARIKAI ,  Akihiro ITOU

IPC: H01L21/311 ,  H01L21/78 ,  H01L21/683

Abstract: An etching method including: a preparation step of preparing a resin layer and an electronic component supported thereby; and a resin etching step of etching the resin layer. The electronic component has a first surface covered with a protective film, a second surface opposite thereto, and a sidewall therebetween. The second surface is facing the resin layer. The resin layer is larger than the electronic component when seen from the first surface side. The resin etching step includes: a deposition step of depositing a first film, using a first plasma, on a surface of the protective film and a surface of the resin layer; and a removal step of removing, using a second plasma, the first film deposited on the resin layer and at least part of the resin layer. The deposition and removal steps are alternately repeated, with the protective film allowed to continue to exist.

公开(公告)号：US20190304838A1

公开(公告)日：2019-10-03

申请号：US16362933

申请日：2019-03-25

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidefumi SAEKI ,  Atsushi HARIKAI ,  Shogo OKITA

IPC: H01L21/78 ,  H01L23/544 ,  H01L21/268 ,  H01L21/3065 ,  B23K26/00 ,  B23K26/364

Abstract: A manufacturing process of an element chip comprises a preparing step for preparing a substrate having first and second sides opposed to each other, the substrate containing a semiconductor layer, a wiring layer and a resin layer formed on the first side, and the substrate including a plurality of dicing regions and element regions defined by the dicing regions. Also, the manufacturing process comprises a laser grooving step for irradiating a laser beam onto the dicing regions to form grooves so as to expose the semiconductor layer along the dicing regions. Further, the manufacturing process comprises a dicing step for plasma-etching the semiconductor layer along the dicing regions through the second side to divide the substrate into a plurality of the element chips. The laser grooving step includes a melting step for melting a surface of the semiconductor layer exposed along the dicing regions.

公开(公告)号：US20190066981A1

公开(公告)日：2019-02-28

申请号：US16114467

申请日：2018-08-28

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo OKITA

IPC: H01J37/32 ,  H01L21/683 ,  H01L21/677

Abstract: A plasma processing device has a chamber that can be depressurized, a plasma source to generate plasma in the chamber, a stage in the chamber on which the conveyance carrier is placed, and a cover on the stage to cover a holding sheet and a frame and including a window portion penetrating a thickness direction. The cover includes an introduction port, a discharge port, and a coolant flow path connecting the introduction port and the discharge port and not overlapping with a region on an inner side of the frame in plan view. The stage includes a supply port communicated with the introduction port to allow supply of coolant to the coolant flow path when the cover is on the stage, and a recovery port communicated with the discharge port to allow recovery of coolant supplied to the coolant flow path when the cover is on the stage.