公开(公告)号：US20180090333A1

公开(公告)日：2018-03-29

申请号：US15682814

申请日：2017-08-22

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Noriyuki MATSUBARA

IPC: H01L21/3065 ,  H01L21/32 ,  H01L21/3213

Abstract: A manufacturing process of an elemental chip comprises steps of preparing a substrate held on the holding tape, the substrate including first and second sides opposite each other and the second side thereof being held on the holding tape, and the substrate further including a plurality of element regions and a plurality of segmentation regions defining each of the element regions; spraying a resist solution to form droplets of the resist solution, the resist solution containing a resist constituent and a solvent; forming a resist layer by vaporizing the solvent from the droplets and depositing the resist constituent on the first side of the substrate that is held on the holding tape; patterning the resist layer to expose the first side of the substrate in the segmentation regions; and plasma-etching the first side of the substrate exposed in the segmentation regions thereof.

公开(公告)号：US20190221479A1

公开(公告)日：2019-07-18

申请号：US16246627

申请日：2019-01-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo OKITA ,  Atsushi HARIKAI ,  Noriyuki MATSUBARA ,  Hidefumi SAEKI ,  Akihiro ITOU

IPC: H01L21/78 ,  H01L21/3065 ,  H01L21/683 ,  H01L21/56

CPC classification number: H01L21/78 ,  H01L21/3065 ,  H01L21/561 ,  H01L21/6836

Abstract: A manufacturing process of an element chip comprises steps of preparing a substrate including dicing regions and element regions, attaching a holding sheet held on a frame with a die attach film in between, forming a protective film covering the substrate, forming a plurality of grooves in the protective film along the dicing regions, plasma-etching the substrate to expose the die attach film and then die attach film along the dicing regions, and picking up each of the element chips along with the separated die attach film away from the holding sheet, wherein the die attach film has an area greater than that of the substrate, and wherein the protective film includes a first covering portion covering the substrate and a second covering portion covering at least a portion of the die attach film that extends beyond an outer edge of the substrate.

公开(公告)号：US20180240678A1

公开(公告)日：2018-08-23

申请号：US15899422

申请日：2018-02-20

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Akihiro ITOU ,  Atsushi HARIKAI ,  Noriyuki MATSUBARA ,  Shogo OKITA

IPC: H01L21/3065 ,  H01J37/32 ,  H01L21/687 ,  H01L21/78 ,  H01L21/683

CPC classification number: H01L21/30655 ,  H01J37/00 ,  H01J37/32009 ,  H01J37/3244 ,  H01J37/32743 ,  H01L21/31138 ,  H01L21/67109 ,  H01L21/6835 ,  H01L21/68735 ,  H01L21/68742 ,  H01L21/68785 ,  H01L21/78 ,  H01L21/7806 ,  H01L2221/68327

Abstract: Provided is a manufacturing process of an element chip, which comprises a preparation step, a setting step for setting the substrate on a stage, and a plasma-dicing step for dividing the substrate into a plurality of element chips, wherein the plasma-dicing step is achieved by repeatedly implementing etching routines each including an etching step for etching the second layer along the street regions to form a plurality of grooves and a depositing step for depositing a protective film on inner walls of the grooves, wherein the plasma-dicing step includes a first etching step for forming the grooves each having a first scallop on the inner wall thereof at a first pitch, and a second etching step for forming the grooves each having a second scallop on the inner wall thereof at a second pitch, and wherein the second pitch is greater than the first pitch.

公开(公告)号：US20160064188A1

公开(公告)日：2016-03-03

申请号：US14818415

申请日：2015-08-05

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo OKITA ,  Hiromi ASAKURA ,  Syouzou WATANABE ,  Noriyuki MATSUBARA ,  Mitsuru HIROSHIMA ,  Toshihiro WADA

IPC: H01J37/32

CPC classification number: H01J37/32715 ,  H01J37/32366 ,  H01J37/32733 ,  H01L21/681

Abstract: A plasma processing apparatus that performs plasma processing to a substrate held on a transport carrier including a frame and a holding sheet that covers an opening of the frame includes: a transport mechanism that transports the transport carrier; a position measuring section that measures a position of the substrate to the frame; a plasma processing section that includes a plasma processing stage on which the transport carrier is loaded and a cover that covers the frame and a part of the holding sheet loaded on the plasma processing stage, and has a window section for exposing a part of the substrate; and a control section that controls the transport mechanism such that the transport carrier is loaded on the plasma processing stage to satisfy a positional relationship between the window section and the substrate based on the position information of the substrate to the frame.

Abstract translation: 对保持在包括框架的运送载体上的基板和覆盖框架的开口的保持片进行等离子体处理的等离子体处理装置包括：运送运送托架的运送机构; 位置测量部，其测量所述基板与所述框架的位置; 等离子体处理部，其包括装载有运送载体的等离子体处理台和覆盖框架的盖和负载在等离子体处理台上的保持片的一部分，并具有用于使基板的一部分露出的窗口部 ; 以及控制部，其控制所述输送机构，使得所述输送载体基于所述基板到所述框架的位置信息而被载载在所述等离子体处理台上以满足所述窗口部和所述基板之间的位置关系。

公开(公告)号：US20200098636A1

公开(公告)日：2020-03-26

申请号：US16567047

申请日：2019-09-11

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi HARIKAI ,  Shogo OKITA ,  Noriyuki MATSUBARA ,  Hidefumi SAEKI ,  Akihiro ITOU

IPC: H01L21/78 ,  H01L21/683

Abstract: An element chip manufacturing method including: a preparing step of preparing a first conveying carrier including a holding sheet and a frame, and a substrate held on the holding sheet, the holding sheet having a first surface and a second surface opposite the first surface, the frame attached to at least part of a peripheral edge of the holding sheet; a placing step of placing the first conveying carrier holding the substrate, on a second conveying carrier; a preprocessing step of preprocessing the substrate, after the placing step; a removing step of removing the second conveying carrier, after the preprocessing step; and a dicing step of subjecting the substrate held on the first conveying carrier to plasma exposure, after the removing step, to form a plurality of element chips from the substrate.

公开(公告)号：US20180233395A1

公开(公告)日：2018-08-16

申请号：US15893999

申请日：2018-02-12

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo OKITA ,  Koji TAMURA ,  Akihiro ITOU ,  Atsushi HARIKAI ,  Noriyuki MATSUBARA

IPC: H01L21/683 ,  H01L21/78 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L21/6835 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/6836 ,  H01L21/78 ,  H01L24/12 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2221/68386

Abstract: A method of manufacturing a semiconductor chip includes: preparing a semiconductor wafer; forming a mask on a front surface of the semiconductor wafer so as to cover each of the element regions and to expose the dividing region; exposing the front surface to plasma in a state where a back surface of the semiconductor wafer is held with a dicing tape to dice the semiconductor wafer into a plurality of semiconductor chips by etching the dividing region exposed from the mask up to the back surface while protecting each of the element regions with the mask from plasma; and removing the mask from the front surface together with an adhesive tape by peeling off the adhesive tape after sticking the adhesive tape to the side of the front surface.

公开(公告)号：US20150340208A1

公开(公告)日：2015-11-26

申请号：US14719797

申请日：2015-05-22

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi HARIKAI ,  Noriyuki MATSUBARA ,  Mitsuru HIROSHIMA

IPC: H01J37/32 ,  C23C16/458 ,  C23C16/505

CPC classification number: H01L21/3065 ,  C23C16/455 ,  C23C16/458 ,  C23C16/4583 ,  C23C16/4585 ,  C23C16/4586 ,  C23C16/505 ,  H01J37/32082 ,  H01J37/321 ,  H01J37/3244 ,  H01J37/32651 ,  H01J37/32715 ,  H01J37/32724 ,  H01L21/308 ,  H01L21/67069 ,  H01L21/6831 ,  H01L21/6833

Abstract: A plasma processing method to a substrate includes a first step of mounting a transfer carrier holding the substrate on a stage which is cooled and provided within a processing chamber; a second step of relatively moving the stage and a cover provided above the stage to cover a holding sheet and an annular frame of the transfer carrier with the substrate exposed from a window part formed at the cover, a third step of carrying out plasma processing on the substrate, a fourth step of cooling the cover, and a fifth step of unloading the transfer carrier holding the substrate from the processing chamber.

Abstract translation: 对衬底的等离子体处理方法包括：将保持衬底的转印载体安装在冷却并设置在处理室内的台上的第一步骤; 相对移动舞台的第二步骤和设置在舞台上方的盖子覆盖保持片和转印支架的环形框架，其中衬底从形成在盖子上的窗口部分露出，第三步骤对 基板，冷却盖的第四步骤以及从处理室卸载保持基板的转印载体的第五步骤。

公开(公告)号：US20190122892A1

公开(公告)日：2019-04-25

申请号：US16154930

申请日：2018-10-09

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo OKITA ,  Atsushi HARIKAI ,  Akihiro ITOU ,  Noriyuki MATSUBARA

IPC: H01L21/3065 ,  H01L21/67 ,  H01L21/683 ,  H01L21/687 ,  H01L21/311 ,  H01L21/677

Abstract: Provided is a plasma processing method which comprises steps of preparing a conveying carrier including a holding sheet and a frame provided on a peripheral region of the holding sheet, adhering the substrate on the holding sheet in an inner region inside the peripheral region to hold the substrate on the conveying carrier, sagging the holding sheet in the inner region, setting the conveying carrier on a stage provided within a plasma processing apparatus to contact the holding sheet on the stage so that the holding sheet in the inner region touches the stage before the holding sheet in the peripheral region does, and plasma processing the substrate.

公开(公告)号：US20190006238A1

公开(公告)日：2019-01-03

申请号：US16008280

申请日：2018-06-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Noriyuki MATSUBARA ,  Hidehiko KARASAKI

IPC: H01L21/82 ,  H01L21/683 ,  H01L21/3065 ,  H01L21/67 ,  H01L21/308 ,  B23K26/364

CPC classification number: H01L21/82 ,  B23K26/0622 ,  B23K26/08 ,  B23K26/364 ,  B23K26/402 ,  B23K2101/40 ,  B23K2103/172 ,  B23K2103/42 ,  B23K2103/56 ,  H01L21/30655 ,  H01L21/3081 ,  H01L21/67069 ,  H01L21/67207 ,  H01L21/6833 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327

Abstract: Provided is a manufacturing process of an element chip, which comprises a preparing step for preparing a substrate containing element regions and dicing regions, a holding step for holding the substrate and a frame with a holding sheet, an applicating step for applying a resin material solution containing a resin constituent and a solvent on the substrate to form a coated layer containing the resin constituent and the solvent thereon, a heating step for heating the substrate held on the holding sheet through a heat shielding member shielding the frame and the holding sheet to substantially remove the solvent from the coated layer, thereby to form a resin layer, a patterning step for patterning the resin layer to expose the substrate in the dicing regions, and a dicing step for dicing the substrate into element chips by plasma-etching the substrate.

公开(公告)号：US20190355586A1

公开(公告)日：2019-11-21

申请号：US16528936

申请日：2019-08-01

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Noriyuki MATSUBARA

IPC: H01L21/3065 ,  H01L21/3213 ,  H01L21/027 ,  H01L21/78 ,  H01L21/683 ,  H01L21/32 ,  H01L21/308 ,  G03F7/039 ,  H01L21/311 ,  G03F7/09

Abstract: A manufacturing process of an elemental chip includes steps of preparing a substrate held on the holding tape, the substrate including first and second sides opposite each other and the second side thereof being held on the holding tape, and the substrate further including a plurality of element regions and a plurality of segmentation regions defining each of the element regions; setting a nozzle to have a length between a lower most edge of the nozzle and the first side of the substrate in a range between 20 mm and 150 mm, spraying a resist solution to form droplets of the resist solution, the resist solution containing a resist constituent and a solvent; forming a resist layer by vaporizing the solvent from the droplets and depositing the resist constituent on the first side of the substrate that is held on the holding tape such that an amount of the solvent remained in the resist layer to be in a range between 5 wt. % and 20 wt. %; patterning the resist layer to expose the first side of the substrate in the segmentation regions; and plasma-etching the first side of the substrate exposed in the segmentation regions thereof.