公开(公告)号：US09236292B2

公开(公告)日：2016-01-12

申请号：US14133262

申请日：2013-12-18

申请人： Patricio E. Romero ,  Scott B. Clendenning ,  Jeanette M. Roberts ,  Florian Gstrein

发明人： Patricio E. Romero ,  Scott B. Clendenning ,  Jeanette M. Roberts ,  Florian Gstrein

IPC分类号： H01L21/768

CPC分类号： H01L21/76897 ,  C23C16/04 ,  C23C16/18 ,  C23C16/45525 ,  H01L21/28506 ,  H01L21/28562 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76849 ,  H01L21/76879

摘要： Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a metallization structure for an integrated circuit involves forming an exposed surface above a substrate, the exposed surface including regions of exposed dielectric material and regions of exposed metal. The method also involves forming, using a selective metal deposition process, a metal layer on the regions of exposed metal without forming the metal layer on the regions of exposed dielectric material.

摘要翻译： 描述了通过原子层沉积（ALD）和化学气相沉积（CVD）来选择性地沉积金属膜。 在一个示例中，制造用于集成电路的金属化结构的方法包括在衬底上形成暴露表面，暴露的表面包括暴露的介电材料的区域和暴露的金属的区域。 该方法还涉及使用选择性金属沉积工艺在暴露的金属的区域上形成金属层，而不在暴露的电介质材料的区域上形成金属层。

公开(公告)号：US20150093890A1

公开(公告)日：2015-04-02

申请号：US14040109

申请日：2013-09-27

申请人： James M. Blackwell ,  Scott B. Clendenning ,  John J. Plombon ,  Patricio E. Romero

发明人： James M. Blackwell ,  Scott B. Clendenning ,  John J. Plombon ,  Patricio E. Romero

IPC分类号： H01L21/285 ,  H01L29/45

CPC分类号： H01L21/76843 ,  C07F15/06 ,  C23C16/06 ,  C23C16/16 ,  C23C16/18 ,  C23C16/45553 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76898

摘要： A metal precursor and a method comprising decomposing a metal precursor on an integrated circuit device; and forming a metal from the metal precursor, wherein the metal precursor is selected from the group consisting of (i) a Co2(CO)6(R1C≡CR2), wherein R1 and R2 are individually selected from a straight or branched monovalent hydrocarbon group have one to six carbon atoms that may be interrupted and substituted; (ii) a mononuclear cobalt carbonyl nitrosyl; (iii) a cobalt carbonyl bonded to one of a boron, indium, germanium and tin moiety; (iv) a cobalt carbonyl bonded to a mononuclear or binuclear allyl; and (v) a cobalt (II) complex comprising nitrogen-based supporting ligands.

摘要翻译： 金属前体和包括在集成电路器件上分解金属前体的方法; 以及从所述金属前体形成金属，其中所述金属前体选自（i）Co 2（CO）6（R 1C≡CR2）），其中R 1和R 2分别选自直链或支链一价烃基 具有1-6个可被中断和取代的碳原子; （ii）羰基亚硝酰基单核羰基; （iii）键合到硼，铟，锗和锡部分之一的羰基钴; （iv）键合到单核或双核烯丙基的羰基钴; 和（v）包含氮基支持配体的钴（II）络合物。

公开(公告)号：US20140117559A1

公开(公告)日：2014-05-01

申请号：US13997577

申请日：2012-03-30

申请人： Paul A. Zimmerman ,  Scott B. Clendenning ,  Patricio E. Romero ,  Paul B. Fischer ,  Robert Edgeworth

发明人： Paul A. Zimmerman ,  Scott B. Clendenning ,  Patricio E. Romero ,  Paul B. Fischer ,  Robert Edgeworth

IPC分类号： H01L23/64 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/02205 ,  H01L21/0228 ,  H01L21/76831 ,  H01L21/76837 ,  H01L21/76841 ,  H01L21/76871 ,  H01L21/76879 ,  H01L23/481 ,  H01L23/60 ,  H01L23/642 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06544

摘要： Techniques are disclosed for forming through-silicon vias (TSVs) implementing a negative thermal expansion (NTE) material such as zirconium tungstate (ZrW2O8) or hafnium tungstate (HfW2O8). In some cases, the NTE material is disposed between the substrate and conductive core material of the TSV and serves to offset, at least in part, the coefficient of thermal expansion (CTE) mismatch there between, thus reducing heat-induced stresses and/or protrusion (pumping) of the conductive core material. The NTE material also may protect against leakage, voltage breakdown, and/or diffusion of the conductive core material. Furthermore, the NTE material may reduce radial stresses in high-aspect-ratio TSVs. In some cases, techniques disclosed herein may improve TSV reliability, enhance three-dimensional integration, and/or enhance performance in three-dimensional integrated circuits and/or other three-dimensional packages. Other embodiments which can employ techniques described herein will be apparent in light of this disclosure.

摘要翻译： 公开了形成实现负热膨胀（NTE）材料如钨酸锆（ZrW2O8）或钨酸铪（HfW2O8）的穿硅通孔（TSV）的技术。 在一些情况下，NTE材料设置在TSV的衬底和导电芯材之间，并且用于至少部分地抵消其间的热膨胀系数（CTE）失配，从而减少热诱导的应力和/或 突出（泵送）导电芯材料。 NTE材料还可以防止导电芯材料的泄漏，电压击穿和/或扩散。 此外，NTE材料可以降低高纵横比TSV中的径向应力。 在一些情况下，本文公开的技术可以提高三维集成电路和/或其他三维封装中的TSV可靠性，增强三维集成和/或增强性能。 根据本公开，可以使用本文描述的技术的其它实施例将是显而易见的。

公开(公告)号：US20130270513A1

公开(公告)日：2013-10-17

申请号：US13977601

申请日：2011-09-29

申请人： Patricio E. Romero ,  Scott B. Clendenning

发明人： Patricio E. Romero ,  Scott B. Clendenning

IPC分类号： H01L21/285 ,  H01L29/45 ,  H01L29/49

CPC分类号： H01L21/28556 ,  C23C16/30 ,  C23C16/42 ,  H01L21/28506 ,  H01L21/28562 ,  H01L21/28575 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53266 ,  H01L29/04 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/161 ,  H01L29/201 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/49 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66522 ,  H01L29/66568 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the present invention provide methods for forming layers that comprise electropositive metals through ALD (atomic layer deposition) and or CVD (chemical vapor deposition) processes, layers comprising one or more electropositive metals, and semiconductor devices comprising layers comprising one or more electropositive metals. In embodiments of the invention, the layers are thin or ultrathin (films that are less than 100 {acute over (Å)} thick) and or conformal films. Additionally provided are transistor devices, metal interconnects, and computing devices comprising metal layers comprising one or more electropositive metals.

摘要翻译： 本发明的实施方案提供了通过ALD（原子层沉积）和/或CVD（化学气相沉积）工艺形成包含正电性金属的层的方法，包括一种或多种正电性金属的层以及包含一种或多种正电性金属的层的半导体器件 。 在本发明的实施方案中，这些层是薄的或超薄的（薄膜小于100（厚度超过（）}）和/或保形膜。 另外提供的是晶体管器件，金属互连和包括包含一种或多种正电性金属的金属层的计算器件。

公开(公告)号：US09583389B2

公开(公告)日：2017-02-28

申请号：US14960104

申请日：2015-12-04

申请人： Patricio E. Romero ,  Scott B. Clendenning ,  Jeanette M. Roberts ,  Florian Gstrein

发明人： Patricio E. Romero ,  Scott B. Clendenning ,  Jeanette M. Roberts ,  Florian Gstrein

IPC分类号： H01L21/768 ,  H01L21/285 ,  C23C16/04 ,  C23C16/18 ,  C23C16/455

CPC分类号： H01L21/76897 ,  C23C16/04 ,  C23C16/18 ,  C23C16/45525 ,  H01L21/28506 ,  H01L21/28562 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76849 ,  H01L21/76879

摘要： Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a metallization structure for an integrated circuit involves forming an exposed surface above a substrate, the exposed surface including regions of exposed dielectric material and regions of exposed metal. The method also involves forming, using a selective metal deposition process, a metal layer on the regions of exposed metal without forming the metal layer on the regions of exposed dielectric material.

摘要翻译： 描述了通过原子层沉积（ALD）和化学气相沉积（CVD）来选择性地沉积金属膜。 在一个示例中，制造用于集成电路的金属化结构的方法包括在衬底上形成暴露表面，暴露的表面包括暴露的介电材料的区域和暴露的金属的区域。 该方法还涉及使用选择性金属沉积工艺在暴露的金属的区域上形成金属层，而不在暴露的电介质材料的区域上形成金属层。

公开(公告)号：US20160086850A1

公开(公告)日：2016-03-24

申请号：US14960104

申请日：2015-12-04

申请人： Patricio E. Romero ,  Scott B. Clendenning ,  Jeanette M. Roberts ,  Florian Gstrein

发明人： Patricio E. Romero ,  Scott B. Clendenning ,  Jeanette M. Roberts ,  Florian Gstrein

IPC分类号： H01L21/768 ,  H01L21/285

CPC分类号： H01L21/76897 ,  C23C16/04 ,  C23C16/18 ,  C23C16/45525 ,  H01L21/28506 ,  H01L21/28562 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76849 ,  H01L21/76879

摘要： Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a metallization structure for an integrated circuit involves forming an exposed surface above a substrate, the exposed surface including regions of exposed dielectric material and regions of exposed metal. The method also involves forming, using a selective metal deposition process, a metal layer on the regions of exposed metal without forming the metal layer on the regions of exposed dielectric material.

公开(公告)号：US20150176119A1

公开(公告)日：2015-06-25

申请号：US14134087

申请日：2013-12-19

申请人： James M. Blackwell ,  Daniel B. Bergstrom ,  Scott B. Clendenning ,  Patricio E. Romero

发明人： James M. Blackwell ,  Daniel B. Bergstrom ,  Scott B. Clendenning ,  Patricio E. Romero

IPC分类号： C23C16/06

CPC分类号： C23C16/18

摘要： Methods of forming cobalt films utilizing a cobalt precursor comprising an additive are described. Those methods may include adding an additive to a cobalt precursor, wherein the cobalt precursor is located in an ampoule that is coupled with a deposition tool, and then forming a cobalt film using the cobalt precursor comprising the additive. Non-volatile decomposition products of the cobalt precursor are solubilized in the ampoule.

摘要翻译： 描述了使用包含添加剂的钴前体形成钴膜的方法。 这些方法可以包括将添加剂添加到钴前体中，其中钴前体位于与沉积工具耦合的安瓿中，然后使用包含添加剂的钴前体形成钴膜。 钴前体的非挥发性分解产物溶解在安瓿中。

公开(公告)号：US09385033B2

公开(公告)日：2016-07-05

申请号：US14040109

申请日：2013-09-27

申请人： James M. Blackwell ,  Scott B. Clendenning ,  John J. Plombon ,  Patricio E. Romero

发明人： James M. Blackwell ,  Scott B. Clendenning ,  John J. Plombon ,  Patricio E. Romero

IPC分类号： H01L21/06 ,  H01L21/768 ,  C07F15/06 ,  C23C16/06 ,  C23C16/16 ,  C23C16/18 ,  C23C16/455 ,  H01L21/285

CPC分类号： H01L21/76843 ,  C07F15/06 ,  C23C16/06 ,  C23C16/16 ,  C23C16/18 ,  C23C16/45553 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76898

摘要： A metal precursor and a method comprising decomposing a metal precursor on an integrated circuit device; and forming a metal from the metal precursor, wherein the metal precursor is selected from the group consisting of (i) a Co2(CO)6(R1C≡CR2), wherein R1 and R2 are individually selected from a straight or branched monovalent hydrocarbon group have one to six carbon atoms that may be interrupted and substituted; (ii) a mononuclear cobalt carbonyl nitrosyl; (iii) a cobalt carbonyl bonded to one of a boron, indium, germanium and tin moiety; (iv) a cobalt carbonyl bonded to a mononuclear or binuclear allyl; and (v) a cobalt(II) complex comprising nitrogen-based supporting ligands.

摘要翻译： 金属前体和包括在集成电路器件上分解金属前体的方法; 以及从所述金属前体形成金属，其中所述金属前体选自（i）Co 2（CO）6（R 1C≡CR2）），其中R 1和R 2分别选自直链或支链一价烃基 具有1-6个可被中断和取代的碳原子; （ii）羰基亚硝酰基单核羰基; （iii）键合到硼，铟，锗和锡部分之一的羰基钴; （iv）键合到单核或双核烯丙基的羰基钴; 和（v）包含氮基支持配体的钴（II）络合物。

公开(公告)号：US20150170961A1

公开(公告)日：2015-06-18

申请号：US14133262

申请日：2013-12-18

申请人： Patricio E. Romero ,  Scott B. Clendenning ,  Jeanette M. Roberts ,  Florian Gstrein

发明人： Patricio E. Romero ,  Scott B. Clendenning ,  Jeanette M. Roberts ,  Florian Gstrein

IPC分类号： H01L21/768

CPC分类号： H01L21/76897 ,  C23C16/04 ,  C23C16/18 ,  C23C16/45525 ,  H01L21/28506 ,  H01L21/28562 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76849 ,  H01L21/76879

摘要： Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a metallization structure for an integrated circuit involves forming an exposed surface above a substrate, the exposed surface including regions of exposed dielectric material and regions of exposed metal. The method also involves forming, using a selective metal deposition process, a metal layer on the regions of exposed metal without forming the metal layer on the regions of exposed dielectric material.

摘要翻译： 描述了通过原子层沉积（ALD）和化学气相沉积（CVD）来选择性地沉积金属膜。 在一个示例中，制造用于集成电路的金属化结构的方法包括在衬底上形成暴露表面，暴露的表面包括暴露的介电材料的区域和暴露的金属的区域。 该方法还涉及使用选择性金属沉积工艺在暴露的金属的区域上形成金属层，而不在暴露的电介质材料的区域上形成金属层。

公开(公告)号：US08952355B2

公开(公告)日：2015-02-10

申请号：US13977601

申请日：2011-09-29

申请人： Patricio E. Romero ,  Scott B. Clendenning

发明人： Patricio E. Romero ,  Scott B. Clendenning

IPC分类号： H01L29/06 ,  H01L21/285 ,  H01L29/78 ,  H01L29/786 ,  H01L29/49 ,  H01L29/45 ,  H01L21/768 ,  C23C16/30 ,  C23C16/42

CPC分类号： H01L21/28556 ,  C23C16/30 ,  C23C16/42 ,  H01L21/28506 ,  H01L21/28562 ,  H01L21/28575 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53266 ,  H01L29/04 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/161 ,  H01L29/201 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/49 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66522 ,  H01L29/66568 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the present invention provide methods for forming layers that comprise electropositive metals through ALD (atomic layer deposition) and or CVD (chemical vapor deposition) processes, layers comprising one or more electropositive metals, and semiconductor devices comprising layers comprising one or more electropositive metals. In embodiments of the invention, the layers are thin or ultrathin (films that are less than 100 {acute over (Å)} thick) and or conformal films. Additionally provided are transistor devices, metal interconnects, and computing devices comprising metal layers comprising one or more electropositive metals.

摘要翻译： 本发明的实施方案提供了通过ALD（原子层沉积）和/或CVD（化学气相沉积）工艺形成包含正电性金属的层的方法，包括一种或多种正电性金属的层以及包含一种或多种正电性金属的层的半导体器件 。 在本发明的实施方案中，这些层是薄的或超薄的（薄膜小于100（厚度超过（）}）和/或保形膜。 另外提供的是晶体管器件，金属互连和包括包含一种或多种正电性金属的金属层的计算器件。