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公开(公告)号：US06665525B2
公开(公告)日：2003-12-16
申请号：US09866934
申请日：2001-05-29
IPC分类号： H04B102
CPC分类号： H03F1/0222 , H03F2200/331 , H03F2200/462 , H03F2200/471 , H03F2200/504
摘要： Methods and systems for amplitude-modulating a power amplifier based on sensed current and sensed voltage provided to the power amplifier are provided. The sensed current and sensed voltage may be summed to provided both current and voltage feedback to modulate the power supplied to the power amplifier. Alternatively, both the current feedback and the voltage feedback may be selectively utilized to modulate the power supplied to the power amplifier.
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公开(公告)号：US06768391B1
公开(公告)日：2004-07-27
申请号：US09602385
申请日：2000-06-22
IPC分类号： H03C100
CPC分类号： H03C3/40 , H03D7/1441 , H03D7/1458 , H03D7/1491 , H03D7/165 , H03D2200/0033 , H03D2200/0043
摘要： Quadrature modulators include a quadrature splitter and a pair of Gilbert Multiplier Cells coupled to the quadrature splitter, each of which is biased in Class-B. The quiescent current bias in the Gilbert Multiplier Cells may be substantially zero. Each of the Gilbert Multiplier Cells may include a pair of cross-coupled, emitter-coupled transistor pairs transistor pairs and a driver circuit that is coupled to at least one of the emitter-coupled transistor pairs and that is biased in Class-B. The driver circuit may include at least one current mirror circuit that is coupled to at least one of the emitter-coupled transistor pairs. The driver circuit also may include at least one current source that selectively applies current to at least one of the emitter-coupled transistor pairs, more specifically by selectively applying current to the at least one current mirror circuit.
摘要翻译： 正交调制器包括正交分离器和耦合到正交分离器的一对吉尔伯特乘法器单元，其中每一个在B类中被偏置。 吉尔伯特乘法器单元中的静态电流偏置可以基本为零。 吉尔伯特乘法器单元中的每一个可以包括一对交叉耦合的发射极耦合晶体管对以及耦合到发射极耦合晶体管对中的至少一个并且在B类中偏置的驱动器电路。 驱动器电路可以包括耦合到发射极耦合晶体管对中的至少一个的至少一个电流镜电路。 驱动器电路还可以包括至少一个电流源，其选择性地向至少一个发射极耦合晶体管对施加电流，更具体地，通过选择性地将电流施加到至少一个电流镜电路。
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公开(公告)号：US07072421B2
公开(公告)日：2006-07-04
申请号：US09746823
申请日：2000-12-22
IPC分类号： H04L27/36
CPC分类号： H03F3/24 , H03C3/0941 , H03C3/0966 , H03C3/0983 , H03C3/40 , H03F2200/336 , H03F2200/504 , H04L27/362
摘要： A digital signal processor generates in-phase, quadrature-phase and amplitude signals from a baseband signal. A modulator modulates the in-phase and quadrature-phase signals to produce a modulated signal. A phase locked loop is responsive to the modulated signal. The phase locked loop includes a controlled oscillator having a controlled oscillator input. An amplifier includes a signal input, amplitude control input and an output. The signal input is responsive to the controlled oscillator output and the amplitude control input is responsive to the amplitude signal. The phase locked loop that is responsive to the modulated signal includes a controlled oscillator output and a feedback loop between the controlled oscillator input and the controlled oscillator output. The feedback loop includes a mixer that is responsive to a local oscillator. The modulator may be placed in the phase locked loop. In particular, the modulator may be placed in the feedback loop between the controlled oscillator output and the mixer, between the local oscillator and the mixer, or between the mixer and the controlled oscillator input.
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公开(公告)号：US5847623A
公开(公告)日：1998-12-08
申请号：US925572
申请日：1997-09-08
CPC分类号： H03C1/545 , H03C3/40 , H03C1/02 , H03C2200/0012 , H03C2200/002 , H03C2200/0025 , H03C2200/0058
摘要： A Gilbert Multiplier Cell includes an emitter-coupled transistor pair and a pair of cross-coupled emitter-coupled transistor pairs. A filter couples the emitter-coupled transistor pair to the pair of the cross-coupled emitter-coupled transistor pairs. The filter may include a pair of inductors or resistors, a respective one of which serially couples a respective one of the emitter-coupled transistor pair to a respective one of the pair of cross-coupled emitter-coupled transistor pairs, and a capacitor connected between the pair of inductors or resistors. A local oscillator is coupled to the pair of cross-coupled emitter-coupled transistor pairs and a data input is coupled to the emitter-coupled transistor pair. By low pass filtering the output of the emitter-coupled transistor pair that is applied to the pair of cross-coupled emitter-coupled transistor pairs, low noise floor Gilbert Multiplier Cells and quadraphase modulators may be provided.
摘要翻译： 吉尔伯特乘法器单元包括发射极耦合晶体管对和一对交叉耦合发射极耦合晶体管对。 一个滤波器将发射极耦合晶体管对耦合到一对交叉耦合的发射极耦合晶体管对。 滤波器可以包括一对电感器或电阻器，其中相应的一个电感器或电阻器将发射极耦合晶体管对中的相应一个串联耦合到该对交叉耦合发射极耦合晶体管对中的相应一个，以及连接在 一对电感器或电阻器。 本地振荡器耦合到一对交叉耦合发射极耦合晶体管对，并且数据输入耦合到发射极耦合晶体管对。 通过对施加到一对交叉耦合发射极耦合晶体管对的发射极耦合晶体管对的输出进行低通滤波，可以提供低噪声基底吉尔伯特乘法器单元和四图形调制器。
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公开(公告)号：US07072626B2
公开(公告)日：2006-07-04
申请号：US10426510
申请日：2003-04-30
IPC分类号： H04B1/04
CPC分类号： H03F3/24 , H03F1/0211 , H03F2200/331 , H03F2200/504 , H04L27/361 , H04L27/368
摘要： A polar modulation transmitter circuit provides reduced ACPR in its output signal by controlling the relative delay between its envelope and phase modulation operations based on direct or indirect feedback measurement the output signal's ACPR. Such measurement and associated control may be based on a delay controller that includes an ACPR measurement circuit and a delay control circuit. Additionally, or alternatively, the polar modulation transmitter circuit provides a greatly extended transmit power control range by using a staged amplifier circuit that includes a driver amplifier circuit operating in combination with a power amplifier circuit to impart desired envelope modulation. In an exemplary embodiment, the driver amplifier circuit is implemented as differential transistor pairs responsive to tail current modulation. As such, the driver amplifier circuit is suited in particular for economical and space saving integration within a transmitter or transceiver integrated circuit (IC).
摘要翻译： 极性调制发射机电路通过基于对输出信号的ACPR的直接或间接反馈测量来控制其包络和相位调制操作之间的相对延迟来在其输出信号中提供减小的ACPR。 这种测量和相关控制可以基于包括ACPR测量电路和延迟控制电路的延迟控制器。 另外或者替代地，极坐标调制发射机电路通过使用分段放大器电路提供了大大扩展的发射功率控制范围，分级放大器电路包括与功率放大器电路组合工作的驱动放大器电路，以实现期望的包络调制。 在示例性实施例中，驱动器放大器电路被实现为响应于尾电流调制的差分晶体管对。 因此，驱动放大器电路特别适用于发射机或收发器集成电路（IC）内经济和节省空间的集成。
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6.发明授权IQ modulation systems and methods that use separate phase and amplitude signal paths 有权IQ调制系统和方法使用单独的相位和幅度信号路径公开(公告)号：US06975686B1
公开(公告)日：2005-12-13
申请号：US09703037
申请日：2000-10-31
申请人： M. Ali Khatibzadeh , Aristotle Hadjichristos , Scott R. Justice , Steven G. Cairns , Charles Gore, Jr. , Jeffrey Schlang , Erik Bengtsson , William O. Camp, Jr. , David R. Pehlke
发明人： M. Ali Khatibzadeh , Aristotle Hadjichristos , Scott R. Justice , Steven G. Cairns , Charles Gore, Jr. , Jeffrey Schlang , Erik Bengtsson , William O. Camp, Jr. , David R. Pehlke
CPC分类号： H03F3/24 , H03C3/0941 , H03C3/0966 , H03C3/0983 , H03C3/40 , H03F2200/336 , H03F2200/504 , H04L27/362
摘要： A digital signal processor generates in-phase, quadrature-phase and amplitude signals from a baseband signal. A modulator modulates the in-phase and quadrature-phase signals to produce a modulated signal. A phase locked loop is responsive to the modulated signal. The phase locked loop includes a controlled oscillator having a controlled oscillator input. An amplifier includes a signal input, amplitude control input and an output. The signal input is responsive to the controlled oscillator output and the amplitude control input is responsive to the amplitude signal. The in-phase and quadrature-phase signals may be normalized in-phase and quadrature-phase signals. Alternatively, a phase tracking subsystem may be provided that is responsive to the quadrature modulator to produce a phase signal that is responsive to phase changes in the modulated signal and that is independent of amplitude changes in the modulated signal. An amplitude tracking subsystem also may be provided that is responsive to the modulator to produce an amplitude system that is responsive to amplitude changes in the modulated signal and that is independent of the phase changes in the modulated signal. An amplifier has a signal output, an amplitude control input and an output. The signal input is responsive to the phase signal and the amplitude control input is responsive to the amplitude signal.
摘要翻译： 数字信号处理器从基带信号产生同相，正交相位和幅度信号。 调制器调制同相和正交相位信号以产生调制信号。 锁相环对调制信号作出响应。 锁相环包括具有受控振荡器输入的受控振荡器。 放大器包括信号输入，幅度控制输入和输出。 信号输入响应于受控振荡器输出，并且幅度控制输入响应振幅信号。 同相和正交相信号可以是归一化的同相和正交相位信号。 或者，可以提供响应于正交调制器的相位跟踪子系统，以产生响应于调制信号中的相位变化并且与调制信号中的幅度变化无关的相位信号。 还可以提供振幅跟踪子系统，其响应于调制器产生响应于调制信号中的幅度变化并且与调制信号中的相位变化无关的振幅系统。 放大器具有信号输出，幅度控制输入和输出。 信号输入响应于相位信号，幅度控制输入响应振幅信号。
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公开(公告)号：US08971830B2
公开(公告)日：2015-03-03
申请号：US12575414
申请日：2009-10-07
申请人： Aristotle Hadjichristos , Puay Hoe See , Babak Nejati , Guy Klemens , Norman L Frederick, Jr. , Gurkanwal S Sahota , Marco Cassia , Nathan M Pletcher , Yu Zhao , Thomas A Myers
发明人： Aristotle Hadjichristos , Puay Hoe See , Babak Nejati , Guy Klemens , Norman L Frederick, Jr. , Gurkanwal S Sahota , Marco Cassia , Nathan M Pletcher , Yu Zhao , Thomas A Myers
CPC分类号： H04B1/0458 , H03F1/0277 , H03F3/24 , H03F3/72 , H03F2203/7236 , H04B1/0483
摘要： A multi-mode multi-band power amplifier (PA) module is described. In an exemplary design, the PA module includes multiple power amplifiers, multiple matching circuits, and a set of switches. Each power amplifier provides power amplification for its input signal when selected. Each matching circuit provides impedance matching and filtering for its power amplifier and provides a respective output signal. The switches configure the power amplifiers to support multiple modes, with each mode being for a particular radio technology. Each power amplifier supports at least two modes. The PA module may further include a driver amplifier and an additional matching circuit. The driver amplifier amplifies an input signal and provides an amplified signal to the power amplifiers. The additional matching circuit combines the outputs of other matching circuits and provides an output signal with higher output power. The driver amplifier and the power amplifiers can support multiple output power levels.
摘要翻译： 描述了多模式多频带功率放大器（PA）模块。 在示例性设计中，PA模块包括多个功率放大器，多个匹配电路和一组开关。 每个功率放大器在选择时为其输入信号提供功率放大。 每个匹配电路为其功率放大器提供阻抗匹配和滤波，并提供相应的输出信号。 这些开关配置功率放大器以支持多种模式，每种模式都适用于特定的无线电技术。 每个功率放大器至少支持两种模式。 PA模块还可以包括驱动器放大器和附加匹配电路。 驱动器放大器放大输入信号并向功率放大器提供放大的信号。 附加匹配电路组合其他匹配电路的输出，并提供具有较高输出功率的输出信号。 驱动器放大器和功率放大器可以支持多个输出功率电平。
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公开(公告)号：US06839549B2
公开(公告)日：2005-01-04
申请号：US09738971
申请日：2000-12-14
CPC分类号： H03F3/602 , H03F1/0266 , H03F2200/504
摘要： A radio frequency power amplifier circuit provides linear amplitude modulation of a radio frequency output signal while operating in a saturated amplification mode. The power amplifier circuit incorporates a lossy modulator that functions as a variable resistance responsive to an amplitude modulation signal. A supply voltage is coupled to the voltage supply input of the power amplifier circuit through the lossy modulator, such that the supply voltage applied to the power amplifier varies with the amplitude modulation signal. The radio frequency power amplifier circuit modulates the envelope of an RF output signal generated by saturated mode amplification of a constant envelope radio frequency input signal.
摘要翻译： 射频功率放大器电路在以饱和放大模式工作时提供射频输出信号的线性幅度调制。 功率放大器电路包括有损调制器，其响应于幅度调制信号而用作可变电阻。 电源电压通过有损调制器耦合到功率放大器电路的电压源输入，使得施加到功率放大器的电源电压随着幅度调制信号而变化。 射频功率放大器电路调制由恒定包络射频输入信号的饱和模式放大产生的RF输出信号的包络。
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公开(公告)号：US5890051A
公开(公告)日：1999-03-30
申请号：US42554
申请日：1998-03-17
CPC分类号： H04B1/0057 , H03D7/163 , H04B1/005 , H04B1/006 , H04B1/405
摘要： According to a second embodiment of the invention, a mobile phone receiver comprises a first down converter using a first local oscillator frequency which can be tuned in frequency steps by a programmable digital frequency synthesizer PLL which is locked to a reference frequency. The first down converter converts received signals to a first IF for filtering. A second down converter using a second local oscillator converts first IF signals to a second IF. The second local oscillator frequency is generated using a second digital frequency synthesizer PLL which locks the second oscillator to the reference frequency. A third down converter mixes the transmit frequency with the first local oscillator frequency to produce a lock frequency. A third digital frequency synthesizer PLL compares the lock frequency and the reference frequency to control generation of the transmit frequency.
摘要翻译： 根据本发明的第二实施例，移动电话接收机包括使用第一本地振荡器频率的第一下变换器，该第一本地振荡器频率可以通过被锁定到参考频率的可编程数字频率合成器PLL进行频率调节。 第一降压转换器将接收的信号转换为第一IF用于滤波。 使用第二本地振荡器的第二降压转换器将第一IF信号转换为第二IF。 使用将第二振荡器锁定到参考频率的第二数字频率合成器PLL产生第二本地振荡器频率。 第三降压转换器将发射频率与第一本地振荡器频率混合以产生锁频率。 第三数字频率合成器PLL比较锁定频率和参考频率，以控制发射频率的产生。
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