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1.发明授权
公开(公告)号：US4604651A
公开(公告)日：1986-08-05
申请号：US552656
申请日：1983-11-17
CPC分类号： H04N7/0137 , G06T3/40 , H04N3/22 , H04N7/01 , H04N7/0105 , Y10S348/91
摘要： In a television circuit arrangement for field and line frequency doubling and picture part magnification (zooming), in order to obtain the frequency doubling, information is written, alternately, into two field memories (M1, M2) during a field period having line periods at a given writing speed (clock frequency fc), whereby the reading from the field memories takes place at twice the writing speed. For a picture part magnification to be carried out in a simple manner, a magnification control circuit (TG, S3, S4, S11, S12) having a clock signal change-over circuit (S3, S4) is provided, as a result of which during writing, a higher writing speed (clock frequency 2fc) than the said given writing speed (clock frequency fc) is used during a part of the field periods and of the line periods, which part is substantially inversely proportional to the ratio between the higher writing speed and the given writing speed. For intermittent writing, one or more change-over circuits (S11, S12) are provided at the memory signal inputs, which provides, besides a more effective information storage and an improvement of the picture quality, the possibility of movement detection and recursive signal processing for noise reduction.
摘要翻译： 在用于场和线倍频和图像部分放大（缩放）的电视电路装置中，为了获得倍频，信息在具有行周期的场周期期间交替地写入两个场存储器（M1，M2） 给定的写入速度（时钟频率fc），由此来自场存储器的读取以两倍的写入速度进行。 为了简单地进行图像部分放大，提供了具有时钟信号转换电路（S3，S4）的倍率控制电路（TG，S3，S4，S11，S12），其结果是 在写入期间，在场周期和行周期的一部分期间使用比所述给定写入速度（时钟频率fc）更高的写入速度（时钟频率2fc），该部分与较高的时间段之间的比率基本上成反比 写速度和给定的写入速度。 对于间歇写入，在存储器信号输入处提供一个或多个转换电路（S11，S12），除了更有效的信息存储和图像质量的改进之外，提供了移动检测和递归信号处理的可能性 用于降噪。
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2.发明授权
公开(公告)号：US4740842A
公开(公告)日：1988-04-26
申请号：US828937
申请日：1986-02-12
摘要： A movement-adaptive processing circuit for an interlaced video signal has a selection circuit (5) which passes on to its output (21) one of the three video signals applied to its inputs (3, 9, 11) and which signals substantially correspond to three position-sequential lines of two consecutive fields when this signal has an amplitude which is closest to the mean amplitude of these three video signals. The processing circuit may be used many types of circuits such as, for example, in line or field number conversion circuits, noise suppression circuits, DPCM decoding circuits, vertical contour correction circuits and still-picture display circuits of video record players.
摘要翻译： 用于隔行视频信号的移动自适应处理电路具有选择电路（5），该选择电路（5）将施加到其输入（3,9,11）的三个视频信号之一传递到其输出（21），并且哪个信号基本对应于 当该信号具有最接近这三个视频信号的平均幅度的幅度时，两个连续场的三个位置顺序行。 处理电路可以使用诸如线路或场号转换电路，噪声抑制电路，DPCM解码电路，垂直轮廓校正电路和视频记录播放器的静态图像显示电路的多种类型的电路。
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公开(公告)号：US6008849A
公开(公告)日：1999-12-28
申请号：US561572
申请日：1995-11-21
申请人： Peter H. Frencken
发明人： Peter H. Frencken
CPC分类号： H04N19/577 , H04N19/423 , H04N19/427 , H04N19/61
摘要： Presently most MPEG video decoders use 16 Mbit of external memory. This memory capacity is almost completely occupied by the video decoding process in case of 625 line/50 Hz systems. Also the communication speed to the external memory is rather high. In future decoders, additional functions will be added to the video decoder, a need for free memory space and communication bandwidth will come up soon. Memory bandwidth becomes available with the application of synchronous dynamic random access memories (SDRAM) although high memory bandwidths lead to high operating frequencies. In order to release some memory capacity, a modification in the video decoding process is proposed by which 1 up to 3 Mbit of memory capacity can be saved. This modification has no big impact on the memory communication bandwidth. In order to keep the speed requirements in the variable length decoding within practical limits, a 2 step video decoding approach is proposed. On basis of this approach, several alternatives are possible, each with a different trade-off between extra processing requirements and memory saving.
摘要翻译： 目前大多数MPEG视频解码器都使用16 Mbit的外部存储器。 在625线/ 50Hz系统的情况下，该存储器容量几乎完全被视频解码处理占据。 外部存储器的通讯速度也相当高。 在将来的解码器中，附加功能将被添加到视频解码器中，需要空闲的存储器空间和通信带宽将很快出现。 尽管高存储器带宽导致高操作频率，但是随着同步动态随机存取存储器（SDRAM）的应用，存储器带宽变得可用。 为了释放一些存储容量，提出了视频解码过程的修改，可以节省1至3M的存储容量。 这种修改对存储器通信带宽没有大的影响。 为了将可变长度解码中的速度要求保持在实际的限度内，提出了一种2步视频解码方法。 在这种方法的基础上，有几种替代方案是可能的，每种替代方案在额外的处理要求和存储器节省之间具有不同的权衡。
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公开(公告)号：US4926260A
公开(公告)日：1990-05-15
申请号：US345394
申请日：1989-05-01
CPC分类号： H04N5/05
摘要： In order that one clock signal generator in a digital video signal processing circuit comprising a line-coupled clock signal generator and using, for example one or more field memories is sufficient for writing and reading these memories and can still process a signal from a video recorder, the control loop of the clock signal generator uses a comb filter circuit which rapidly corrects regular variations in an output signal of a phase detector of the control loop, which variations are caused by the head drum of the video recorder, without having to adapt the proportioning of a conventional loop filter circuit.
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公开(公告)号：US5936670A
公开(公告)日：1999-08-10
申请号：US836790
申请日：1997-05-19
申请人： Peter H. Frencken
发明人： Peter H. Frencken
CPC分类号： H04N19/427 , H04N19/423 , H04N19/61
摘要： Conventional MPEG decoders require about 16 Mbits of external memory to contain the input buffer, the two usual reference frames, and the B-information. As proposed earlier, about 2,8 Mbit in memory capacity can be saved by omitting the storage of B-information. The system, provides a further exchange between memory capacity and internal processing, to effect MPEG decoding, with only one reference frame stored in memory. All B and P information required for the reconstruction of display information which cannot directly be retrieved from memory is decoded instantaneously. Three decoding sub-steps are provided, a first decoding sub-step for the macroblock parameters, a second decoding sub-step for the picture elements according to a decoding-on-the-fly principle, and a third decoding sub-step for updating of the earlier reference frame after decoding of a later reference frame.
摘要翻译： PCT No.PCT / IB96 / 00959 Sec。 371日期1997年5月19日 102（e）日期1997年5月19日PCT提交1996年9月19日PCT公布。 出版物WO97 / 11562 日期1997年3月27日常规MPEG解码器需要大约16 Mbits的外部存储器来包含输入缓冲器，两个通常的参考帧和B信息。 如前所述，通过省略B信息的存储，可以节省大约2MB的内存容量。 该系统提供了存储器容量和内部处理之间的进一步交换，以仅在存储器中存储一个参考帧来进行MPEG解码。 对于不能直接从存储器检索的显示信息的重建所需的所有B和P信息被瞬时解码。 提供三个解码子步骤，用于宏块参数的第一解码子步骤，根据动态解码原理的图像元素的第二解码子步骤和用于更新的第三解码子步骤 在后面的参考帧解码之后的较早参考帧。
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公开(公告)号：US4947380A
公开(公告)日：1990-08-07
申请号：US208186
申请日：1988-06-16
申请人： Adrianus T. Van Zanten , Hendrikus J. M. Veendrick , Frits A. Steenhof , Peter H. Frencken , Antonius H. H. J. Nillesen , Cornelis G. L. M. Van Der Sanden
发明人： Adrianus T. Van Zanten , Hendrikus J. M. Veendrick , Frits A. Steenhof , Peter H. Frencken , Antonius H. H. J. Nillesen , Cornelis G. L. M. Van Der Sanden
CPC分类号： G11C19/287 , G11C27/04
摘要： The invention relates to a memory device of the charge-coupled shift register type which is subdivided into four sections each of which has a storage capacity of, for example 208,800 bits and which can operate in different modes: parallel-in/parallel-out (as background video memory); 2.times.2 parallel-in, demultiplex/multiplex mode, for example for 100 Hz TV; scan mode; parallel-in-recirculation mode; "shortened" memory, for example for 525-line system, etcetera. Control is realized via a decoding and timing block in which a multi-bit control word is serially input and decoded. In a scan mode (for example, as a teletext memory), the memory sections are scanned one-by-one under the control of a separate scan register in which a scan bit (logic 1) is step-wise shifted until all sections have been read. Via a data output, the scan bit is transferred, for example to the scan register of a further memory device (via its serial data input) which is connected in series with the former memory device.
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