Cleave initiation using varying ion implant dose
    1.
    发明授权
    Cleave initiation using varying ion implant dose 有权
    使用不同的离子注入剂量切割引发

    公开(公告)号:US07820527B2

    公开(公告)日:2010-10-26

    申请号:US12119170

    申请日:2008-05-12

    IPC分类号: H01L21/46

    CPC分类号: H01L21/76254

    摘要: An approach for providing a cleave initiation using a varying ion implant dose is described. In one embodiment, there is a method of forming a substrate. In this embodiment, a semiconductor material is provided and implanted with a spatially varying dose of one or more ion species. A handler substrate is attached to the implanted semiconductor material. A cleave of the implanted semiconductor material is initiated from the handler substrate at a preferential location that is a function of a dose gradient that develops from the spatially varying dose of one or more ion species implanted into the semiconductor material.

    摘要翻译: 描述了使用变化的离子注入剂量提供切割引发的方法。 在一个实施例中,存在形成衬底的方法。 在该实施例中,提供半导体材料并且注入空间变化的一种或多种离子种类的剂量。 处理衬底附着到植入的半导体材料上。 植入的半导体材料的切割在优先位置从处理器基底开始,该优先位置是从植入半导体材料的一种或多种离子物质的空间变化剂量产生的剂量梯度的函数。

    CLEAVE INITIATION USING VARYING ION IMPLANT DOSE
    3.
    发明申请
    CLEAVE INITIATION USING VARYING ION IMPLANT DOSE 有权
    使用变化的离子植入剂进行清洁启动

    公开(公告)号:US20090209084A1

    公开(公告)日:2009-08-20

    申请号:US12119170

    申请日:2008-05-12

    IPC分类号: H01L21/30

    CPC分类号: H01L21/76254

    摘要: An approach for providing a cleave initiation using a varying ion implant dose is described. In one embodiment, there is a method of forming a substrate. In this embodiment, a semiconductor material is provided and implanted with a spatially varying dose of one or more ion species. A handler substrate is attached to the implanted semiconductor material. A cleave of the implanted semiconductor material is initiated from the handler substrate at a preferential location that is a function of a dose gradient that develops from the spatially varying dose of one or more ion species implanted into the semiconductor material

    摘要翻译: 描述了使用变化的离子注入剂量提供切割引发的方法。 在一个实施例中,存在形成衬底的方法。 在该实施例中,提供半导体材料并且注入空间变化的一种或多种离子种类的剂量。 处理衬底附着到植入的半导体材料上。 植入的半导体材料的切割在优先位置从处理器基底开始,该优先位置是从注入到半导体材料中的一种或多种离子种类的空间变化剂量形成的剂量梯度的函数

    UNIFORMITY CONTROL FOR ION BEAM ASSISTED ETCHING
    5.
    发明申请
    UNIFORMITY CONTROL FOR ION BEAM ASSISTED ETCHING 审中-公开
    离子束辅助蚀刻的均匀控制

    公开(公告)号:US20090084757A1

    公开(公告)日:2009-04-02

    申请号:US11863886

    申请日:2007-09-28

    IPC分类号: C23C14/00 B44C1/22

    摘要: An approach for providing uniformity control in an ion beam etch is described. In one embodiment, there is a method for providing uniform etching in an ion beam based etch process. In this embodiment, an ion beam is directed at a surface of a substrate. The surface of the substrate is etched with the ion beam. The etching is controlled to attain uniformity in the etch of the substrate. The control attains uniformity as a function of at least one ion beam based parameter selected from a plurality of ion beam based parameters.

    摘要翻译: 描述了在离子束蚀刻中提供均匀性控制的方法。 在一个实施例中,存在在基于离子束的蚀刻工艺中提供均匀蚀刻的方法。 在本实施例中,离子束被引导到基板的表面。 用离子束蚀刻衬底的表面。 控制蚀刻以在衬底的蚀刻中获得均匀性。 控制获得作为从多个基于离子束的参数中选择的至少一个基于离子束的参数的函数的均匀性。

    Method of producing a high resistivity SIMOX silicon substrate
    6.
    发明授权
    Method of producing a high resistivity SIMOX silicon substrate 失效
    制造高电阻率SIMOX硅衬底的方法

    公开(公告)号:US07112509B2

    公开(公告)日:2006-09-26

    申请号:US10434571

    申请日:2003-05-09

    IPC分类号: H01L21/76

    摘要: The present invention provides a method for generating silicon-on-insulator (SOI) wafers that exhibit a high electrical resistivity. In one embodiment of a method according to the teachings of the invention, a SIMOX process is sandwiched between two Full Oxygen Precipitation (FOP) cycles that sequester interstitial oxygen present in the substrate in the form of oxide precipitates, thereby enhancing the electrical resistivity of the susbtrate.

    摘要翻译: 本发明提供一种产生表现出高电阻率的绝缘体上硅(SOI)晶片的方法。 在根据本发明的教导的方法的一个实施方案中,SIMOX方法夹在两个全氧沉淀(FOP)循环之间,以循环形式存在氧化物沉淀物形式存在于衬底中的间隙氧,由此提高了 susbtrate。

    Internal gettering in SIMOX SOI silicon substrates
    7.
    发明申请
    Internal gettering in SIMOX SOI silicon substrates 失效
    SIMOX SOI硅衬底内部吸杂

    公开(公告)号:US20050037596A1

    公开(公告)日:2005-02-17

    申请号:US10640917

    申请日:2003-08-14

    IPC分类号: H01L21/265 H01L21/322

    CPC分类号: H01L21/26533 H01L21/3226

    摘要: The present invention provides methods for forming SOI wafers having internal gettering layers for sequestering metallic impurities. More particularly, in one embodiment of the invention, a plurality of sites for sequestering metallic impurities are formed in a silicon substrate by implanting a selected dose of oxygen ions therein. In one embodiment, an epitaxial layer of crystalline silicon is formed over the substrate, and a buried continuous oxide layer is generated in the epitaxial layer, for example, by employing a SIMOX process.

    摘要翻译: 本发明提供了形成具有用于隔离金属杂质的内部吸气层的SOI晶片的方法。 更具体地说,在本发明的一个实施例中,通过在其中注入选定剂量的氧离子,在硅衬底中形成多个用于隔离金属杂质的部位。 在一个实施例中,在衬底上形成晶体硅的外延层,并且例如通过使用SIMOX工艺在外延层中产生掩埋的连续氧化物层。

    Internal gettering in SIMOX SOI silicon substrates
    8.
    发明授权
    Internal gettering in SIMOX SOI silicon substrates 失效
    SIMOX SOI硅衬底内部吸杂

    公开(公告)号:US07294561B2

    公开(公告)日:2007-11-13

    申请号:US10640917

    申请日:2003-08-14

    IPC分类号: H01L21/322

    CPC分类号: H01L21/26533 H01L21/3226

    摘要: The present invention provides methods for forming SOI wafers having internal gettering layers for sequestering metallic impurities. More particularly, in one embodiment of the invention, a plurality of sites for sequestering metallic impurities are formed in a silicon substrate by implanting a selected dose of oxygen ions therein. In one embodiment, an epitaxial layer of crystalline silicon is formed over the substrate, and a buried continuous oxide layer is generated in the epitaxial layer, for example, by employing a SIMOX process.

    摘要翻译: 本发明提供了形成具有用于隔离金属杂质的内部吸气层的SOI晶片的方法。 更具体地说,在本发明的一个实施例中,通过在其中注入选定剂量的氧离子,在硅衬底中形成多个用于隔离金属杂质的部位。 在一个实施例中,在衬底上形成晶体硅的外延层,并且例如通过使用SIMOX工艺在外延层中产生掩埋的连续氧化物层。

    TECHNIQUE FOR DEPOSITING METALLIC FILMS USING ION IMPLANTATION SURFACE MODIFICATION FOR CATALYSIS OF ELECTROLESS DEPOSITION
    9.
    发明申请
    TECHNIQUE FOR DEPOSITING METALLIC FILMS USING ION IMPLANTATION SURFACE MODIFICATION FOR CATALYSIS OF ELECTROLESS DEPOSITION 审中-公开
    使用离子植入表面改性沉积金属膜的技术用于电沉积的催化

    公开(公告)号:US20070184194A1

    公开(公告)日:2007-08-09

    申请号:US11672456

    申请日:2007-02-07

    IPC分类号: B05D1/32 B05D1/36

    摘要: Techniques for depositing metallic films using ion implantation surface modification for catalysis of electroless deposition are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for depositing a metallic film. The method may comprise depositing a catalyzing material on a structure, wherein the structure comprises a substrate, a dielectric layer on the substrate, and a resist layer on the dielectric layer, wherein the dielectric layer and the resist layer have one or more openings. The method may also comprise stripping the resist layer. The method may further comprise depositing a metallic film on the catalyzing material in the one or more openings of the structure to fill the one or more openings.

    摘要翻译: 公开了使用离子注入表面改性来沉积非金属沉积催化的金属膜的技术。 在一个特定的示例性实施例中,可以将这些技术实现为用于沉积金属膜的方法。 该方法可以包括在结构上沉积催化材料,其中所述结构包括基底,所述基底上的电介质层和所述电介质层上的抗蚀剂层,其中所述电介质层和所述抗蚀剂层具有一个或多个开口。 该方法还可以包括剥离抗蚀剂层。 该方法还可以包括在结构的一个或多个开口中的催化材料上沉积金属膜以填充一个或多个开口。

    Method and system for forming low contact resistance device
    10.
    发明授权
    Method and system for forming low contact resistance device 有权
    形成低接触电阻器件的方法和系统

    公开(公告)号:US08617955B2

    公开(公告)日:2013-12-31

    申请号:US13181175

    申请日:2011-07-12

    IPC分类号: H01L21/8234

    CPC分类号: H01L21/823807

    摘要: A method of treating a CMOS device. The method may include providing a first stress liner on a transistor of a first dopant type in the CMOS device. The method may further include exposing the CMOS device to first ions in a first exposure, the first ions configured to reduce contact resistance in a source/drain region of a transistor of a second dopant type.

    摘要翻译: 一种处理CMOS器件的方法。 该方法可以包括在CMOS器件中的第一掺杂剂类型的晶体管上提供第一应力衬垫。 该方法还可以包括在第一曝光中将CMOS器件暴露于第一离子,第一离子被配置为降低第二掺杂剂型晶体管的源/漏区中的接触电阻。