公开(公告)号：US4306916A

公开(公告)日：1981-12-22

申请号：US77383

申请日：1979-09-20

Applicant: Donald L. Wollesen ,  William Meuli ,  Philip S. Shiota

Inventor： Donald L. Wollesen ,  William Meuli ,  Philip S. Shiota

IPC: H01L21/76 ,  H01L21/033 ,  H01L21/266 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/08 ,  H01L29/06 ,  H01L29/78 ,  H01L7/54 ,  B01J17/00 ,  H01L21/265

CPC classification number: H01L21/266 ,  H01L21/033 ,  H01L21/76218 ,  H01L21/823807 ,  Y10S438/965

Abstract: A method for fabricating a complementary metal-oxide-silicon (CMOS) integrated circuit device by forming a composite layer of oxide and nitride on the surface of a silicon substrate defined into predetermined areas for the subsequent formation of transistors, masking the substrate to expose preselected areas for P-wells, ion implanting P-type material in the exposed areas to form P-wells so that a relatively high doping level is provided to a greater depth around composite areas within the P-wells areas and a relatively lower doping level is established under the composite layer areas with the P-wells. The ion implantation of P-type material may be accomplished in either a single stage or a two stage procedure.

Abstract translation: 一种用于制造互补金属氧化物 - 硅（CMOS）集成电路器件的方法，其通过在限定到预定区域中的硅衬底的表面上形成氧化物和氮化物的复合层，以便随后形成晶体管，掩蔽衬底以暴露预选 用于P阱的区域，在暴露区域中离子注入P型材料以形成P阱，使得在P阱区域内的复合区域附近提供相对高的掺杂水平，并且相对较低的掺杂水平为 在复合层区域建立了P井。 P型材料的离子注入可以在单阶段或两阶段程序中完成。

公开(公告)号：US06445058B1

公开(公告)日：2002-09-03

申请号：US09573149

申请日：2000-05-17

Applicant: Frank L. Thiel ,  William E. Moore ,  Philip S. Shiota

Inventor： Frank L. Thiel ,  William E. Moore ,  Philip S. Shiota

IPC: H01L27082

CPC classification number: H01L29/402 ,  H01L29/0804 ,  H01L29/7322

Abstract: A semiconductor process is disclosed which forms a field plate structure that integrally contacts an emitter region of a bipolar junction transistor by construction, without intervening interconnect layers or contacts. In one embodiment, a single-layer polysilicon electrode forms a field plate electrode which integrally interconnects to a traditional diffused emitter region formed before the polysilicon layer is deposited. This allows for deeper emitter regions required by the deep base regions needed for high-voltage bipolar devices. Moreover, the polysilicon layer, including the polysilicon electrode forming the field plate electrode, may be used as a local interconnect layer.

Abstract translation: 公开了半导体工艺，其形成通过结构与双极结型晶体管的发射极区域整体接触而不插入互连层或触点的场板结构。 在一个实施例中，单层多晶硅电极形成与在沉积多晶硅层之前形成的传统扩散发射极区域整体互连的场板电极。 这允许高压双极器件所需的深基极区所需的更深的发射极区域。 此外，包括形成场板电极的多晶硅电极的多晶硅层可以用作局部互连层。

公开(公告)号：US06437421B1

公开(公告)日：2002-08-20

申请号：US09573146

申请日：2000-05-17

Applicant: Frank L. Thiel ,  William E. Moore ,  Philip S. Shiota

Inventor： Frank L. Thiel ,  William E. Moore ,  Philip S. Shiota

IPC: H01L27082

CPC classification number: H01L29/6625 ,  H01L21/8222 ,  H01L23/485 ,  H01L27/0823 ,  H01L29/1008 ,  H01L29/735 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor process is disclosed which forms openings in a dielectric layer through which the base region of both high-voltage and high-gain bipolar transistors are formed. In one embodiment of the invention, the openings for the high-gain transistors are first protected by a photoresist layer that is patterned to expose the openings for the high-voltage transistors. A first base implant is performed through the exposed windows in the dielectric layer and into the exposed substrate or epitaxial layer therebelow, and then diffused to a suitable depth. The patterned photoresist is then removed to additionally expose the openings for the high-gain devices, and a second base implant is performed, this time into both base regions, and then diffused to a suitable depth. Emitter regions are then formed within the base regions of both transistor types by traditional implantation and contact techniques. Since the two base implants for each high-voltage transistor are self-aligned to a single opening through the dielectric layer, excellent control and repeatability is achieved for the high-voltage transistors. Moreover, since the second base implant is common to both types of transistors, many of the characteristics of the two types of transistors are well matched to each other.

Abstract translation: 公开了半导体工艺，其在形成高压和高增益双极晶体管的基极区域的电介质层中形成开口。 在本发明的一个实施例中，用于高增益晶体管的开口首先由被图案化以暴露高压晶体管的开口的光致抗蚀剂层保护。 通过介电层中的暴露的窗口进入第一基底植入物，并进入其中暴露的基底或外延层，然后扩散到合适的深度。 然后去除图案化的光致抗蚀剂以另外暴露用于高增益器件的开口，并且此时进行第二基底注入，进入两个基底区域，然后扩散到合适的深度。 然后通过传统的植入和接触技术在两个晶体管类型的基极区域内形成发射极区域。 由于每个高压晶体管的两个基础植入物通过电介质层自对准到单个开口，因此对于高压晶体管实现了优异的控制和可重复性。 此外，由于第二基极注入对于这两种类型的晶体管是共同的，所以两种晶体管的许多特性彼此良好地匹配。

公开(公告)号：US5086011A

公开(公告)日：1992-02-04

申请号：US147892

申请日：1988-01-25

Applicant: Philip S. Shiota

Inventor： Philip S. Shiota

IPC: H01L21/301 ,  H01L21/762

CPC classification number: H01L21/76264 ,  H01L21/76275 ,  H01L21/76281 ,  H01L21/76283 ,  Y10S148/012 ,  Y10S148/135 ,  Y10S438/924 ,  Y10S438/97

Abstract: A semiconductor fabrication process uses an epitaxial layer as an etch stop in a plasma etch process. In one embodiment, mechanical stops and an epitaxial layer are used in combination for stopping precisely at a desired end point.

Abstract translation: 半导体制造工艺在等离子体蚀刻工艺中使用外延层作为蚀刻停止层。 在一个实施例中，机械止动件和外延层组合使用以精确地停止在期望的终点。