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公开(公告)号：US07501974B2
公开(公告)日：2009-03-10
申请号：US11832946
申请日：2007-08-02
IPC分类号： H03M1/12
CPC分类号： H03M1/0682 , H03M1/468 , H03M1/68 , H03M1/804
摘要： An analog/digital converter for converting an analog signal to a digital output code includes a local digital analog converter including a segmented array. The segmented array includes upper and lower segments of conversion elements selectively operable by respective digital command codes for respectively varying, according to binary weighted contributions, the voltages of first and second common nodes and the voltage of a second common node. A logic unit generates the digital command codes for controlling the local digital/analog converter according to a successive approximation technique for producing the digital output code. The converter includes a redistributor for modifying the command codes for redistributing the modified command codes between the lower segment and the upper segment, while making use of at least one auxiliary conversion element provided in the upper segment.
摘要翻译： 用于将模拟信号转换为数字输出代码的模拟/数字转换器包括具有分段阵列的本地数字模拟转换器。 分段阵列包括转换元件的上段和下段，其选择性地由相应的数字命令代码操作，以分别根据二进制加权贡献来改变第一和第二公共节点的电压和第二公共节点的电压。 逻辑单元根据用于产生数字输出代码的逐次逼近技术产生用于控制本地数字/模拟转换器的数字命令代码。 转换器包括再分配器，用于在使用在上段中提供的至少一个辅助转换元件的同时修改用于在下段和上段之间重新分配修改的命令代码的命令代码。
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公开(公告)号：US07158069B2
公开(公告)日：2007-01-02
申请号：US11097456
申请日：2005-04-01
IPC分类号： H03M1/12
摘要： The described analog-digital converter comprises quantization means having an input for receiving an analog quantity to be converted, a register having an output for providing a digital quantity corresponding to the analog quantity, a timing pulse generator and logic means connected to the quantization means, the register and the timing pulse generator and capable of responding to a conversion request signal by activating the quantization means in such a manner as to make them carry out predetermined operations timed by the timing pulses and load into the register the digital quantity to be provided at the output. With a view to permitting the converter to function even when a system clock is not available, the timing pulse generator, which is incorporated in the integrated circuit that comprises the rest of the converter, comprises an oscillator capable of being started/stopped by a binary signal applied to its activation input and the logic means are capable of generating a stop signal of the oscillator and comprise means for generating the binary signal to be applied to the activation input of the oscillator. This signal assumes a first or a second binary state corresponding, respectively, to activation and deactivation of the oscillator in response to, respectively, the conversion request signal and the stop signal of the oscillator.
摘要翻译： 所描述的模拟数字转换器包括具有用于接收要转换的模拟量的输入的量化装置，具有用于提供与模拟量相对应的数字量的输出的寄存器，连接到量化装置的定时脉冲发生器和逻辑装置， 寄存器和定时脉冲发生器，并且能够通过激活量化装置来响应转换请求信号，以使得它们执行由定时脉冲定时的预定操作并将其加载到寄存器中以在 输出。 为了允许转换器即使在系统时钟不可用的情况下也能够运行，包含在转换器的其余部分的集成电路中的定时脉冲发生器包括能够被二进制数进行启动/停止的振荡器 施加到其激活输入的信号，并且逻辑装置能够产生振荡器的停止信号，并且包括用于产生要施加到振荡器的激活输入的二进制信号的装置。 该信号分别响应于转换请求信号和振荡器的停止信号而分别对应于振荡器的激活和去激活的第一或第二二进制状态。
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公开(公告)号：US20050231412A1
公开(公告)日：2005-10-20
申请号：US11097456
申请日：2005-04-01
摘要： The described analog-digital converter comprises quantization means having an input for receiving an analog quantity to be converted, a register having an output for providing a digital quantity corresponding to the analog quantity, a timing pulse generator and logic means connected to the quantization means, the register and the timing pulse generator and capable of responding to a conversion request signal by activating the quantization means in such a manner as to make them carry out predetermined operations timed by the timing pulses and load into the register the digital quantity to be provided at the output. With a view to permitting the converter to function even when a system clock is not available, the timing pulse generator, which is incorporated in the integrated circuit that comprises the rest of the converter, comprises an oscillator capable of being started/stopped by a binary signal applied to its activation input and the logic means are capable of generating a stop signal of the oscillator and comprise means for generating the binary signal to be applied to the activation input of the oscillator. This signal assumes a first or a second binary state corresponding, respectively, to activation and deactivation of the oscillator in response to, respectively, the conversion request signal and the stop signal of the oscillator.
摘要翻译： 所描述的模拟数字转换器包括具有用于接收要转换的模拟量的输入的量化装置，具有用于提供与模拟量相对应的数字量的输出的寄存器，连接到量化装置的定时脉冲发生器和逻辑装置， 寄存器和定时脉冲发生器，并且能够通过激活量化装置来响应转换请求信号，以使得它们执行由定时脉冲定时的预定操作并将其加载到寄存器中以在 输出。 为了允许转换器即使在系统时钟不可用的情况下也能够运行，包含在转换器的其余部分的集成电路中的定时脉冲发生器包括能够被二进制数进行启动/停止的振荡器 施加到其激活输入的信号，并且逻辑装置能够产生振荡器的停止信号，并且包括用于产生要施加到振荡器的激活输入的二进制信号的装置。 该信号分别响应于转换请求信号和振荡器的停止信号而分别对应于振荡器的激活和去激活的第一或第二二进制状态。
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公开(公告)号：US06720903B2
公开(公告)日：2004-04-13
申请号：US10172376
申请日：2002-06-14
IPC分类号： H03M112
摘要： A method of operating an SAR-type analog-to-digital converter to match the dynamic range of an input voltage signal to be converted with the full scale range of the converter, the converter including at least one array of binary weighted capacitors. The method includes the step of obtaining a digital gain code that represents the ratio between the full scale range and the dynamic range of the voltage signal to be converted, applying the voltage signal to be converted to the capacitor array so as to charge with the voltage signal to be converted only those array capacitors having the same binary weights as the bits of the gain code that have a selected binary value, and selectively coupling the capacitors of the array to one of a first and second predetermined reference voltage terminals according to an SAR technique, to obtain an output digital code corresponding to the input voltage signal.
摘要翻译： 一种操作SAR型模数转换器以匹配要转换的输入电压信号的动态范围与转换器的满量程范围的方法，所述转换器包括至少一个二进制加权电容器阵列。 该方法包括获得数字增益代码的步骤，该数字增益代码表示满量程范围和要转换的电压信号的动态范围之间的比率，将要转换的电压信号施加到电容器阵列，以便对电压进行充电 信号仅转换具有与具有选定二进制值的增益码的位相同的二进制权重的阵列电容器，并且根据SAR选择性地将阵列的电容器耦合到第一和第二预定参考电压端子之一 技术，以获得对应于输入电压信号的输出数字代码。
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公开(公告)号：US20080036641A1
公开(公告)日：2008-02-14
申请号：US11832946
申请日：2007-08-02
IPC分类号： H03M1/12
CPC分类号： H03M1/0682 , H03M1/468 , H03M1/68 , H03M1/804
摘要： An analog/digital converter for converting an analog signal to a digital output code includes a local digital analog converter including a segmented array. The segmented array includes upper and lower segments of conversion elements selectively operable by respective digital command codes for respectively varying, according to binary weighted contributions, the voltages of first and second common nodes and the voltage of a second common node. A logic unit generates the digital command codes for controlling the local digital/analog converter according to a successive approximation technique for producing the digital output code. The converter includes a redistributor for modifying the command codes for redistributing the modified command codes between the lower segment and the upper segment, while making use of at least one auxiliary conversion element provided in the upper segment.
摘要翻译： 用于将模拟信号转换为数字输出代码的模拟/数字转换器包括具有分段阵列的本地数字模拟转换器。 分段阵列包括转换元件的上段和下段，其选择性地由相应的数字命令代码操作，以分别根据二进制加权贡献来改变第一和第二公共节点的电压和第二公共节点的电压。 逻辑单元根据用于产生数字输出代码的逐次逼近技术产生用于控制本地数字/模拟转换器的数字命令代码。 转换器包括再分配器，用于在使用在上段中提供的至少一个辅助转换元件的同时修改用于在下段和上段之间重新分配修改的命令代码的命令代码。
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公开(公告)号：US07212143B1
公开(公告)日：2007-05-01
申请号：US11336657
申请日：2006-01-20
IPC分类号： H03M1/12
CPC分类号： H03M1/1225
摘要： A circuit for selectively converting at least one analog signal into corresponding digital codes. The circuit includes a management block having a plurality of inputs, each adapted for receiving a respective request signal carrying a request to convert the at least one analog signal. The management block is adapted to assign a priority level to the request signals based upon the input where the request signals are received, and is further operative to select one of the request signals based upon the assigned priority level and output a conversion start-up signal corresponding to the selected request signal. The circuit has a conversion block for receiving east one analog signal input and is connected to the management block to receive the conversion start-up signal as input, and start up conversion of the at least one analog signal.
摘要翻译： 用于选择性地将至少一个模拟信号转换成相应数字码的电路。 电路包括具有多个输入的管理块，每个输入适于接收携带转换所述至少一个模拟信号的请求的相应请求信号。 管理块适于基于接收到请求信号的输入来为请求信号分配优先级，并且还可操作以基于所分配的优先级来选择一个请求信号，并输出转换启动信号 对应于所选择的请求信号。 电路具有用于接收东一模拟信号输入的转换块，并连接到管理块以接收转换启动信号作为输入，并启动至少一个模拟信号的转换。
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7.发明授权公开(公告)号：US07106237B1
公开(公告)日：2006-09-12
申请号：US11097455
申请日：2005-04-01
IPC分类号： H03M1/12
摘要： The described converter comprises switched-capacitor quantization means for receiving an analog quantity to be converted, a register for a digital quantity corresponding to the analog quantity, a timing pulse generator and logic means capable of responding to a conversion request signal by activating the quantization means in such a way that they will carry out predetermined operations timed by the timing pulses and load in the register the digital quantity to be furnished as output. With a view to saving electric energy during the conversion and reducing the noise induced by the generator, the generator comprises means for modifying the duration and/or the frequency of the timing pulses in response to regulation signals emitted by the logic means. Also described is a method of using the converter that comprises the following phases: loading of the analog quantity in the quantization means, memorization of the loaded analog quantity and identification in the course of successive attempts in accordance with SAR technique of the bits of the digital code corresponding to the analog quantity to be converted. The duration and/or the frequency of the timing pulses are modified during at least one of the phases indicated above in response to regulation signals emitted by the logic means.
摘要翻译： 所描述的转换器包括用于接收要转换的模拟量的开关电容量化装置，对应于模拟量的数字量的寄存器，定时脉冲发生器和能够通过激活量化装置来响应转换请求信号的逻辑装置 以这样的方式，它们将执行由定时脉冲定时的预定操作，并且将寄存器中的负载作为输出提供的数字量。 为了在转换期间节省电能并降低由发生器引起的噪声，发生器包括用于响应于由逻辑装置发出的调节信号而修改定时脉冲的持续时间和/或频率的装置。 还描述了一种使用该转换器的方法，该转换器包括以下阶段：在量化装置中加载模拟量，根据数字位的SAR技术在连续尝试过程中记录加载的模拟量和识别 对应于要转换的模拟量的代码。 响应于由逻辑装置发出的调节信号，定时脉冲的持续时间和/或频率在上述指示的至少一个期间被修改。
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8.发明授权System for processing analog-type electrical signals with low noise driving device 有权具有低噪声驱动装置的模拟型电信号处理系统公开(公告)号：US08427196B2
公开(公告)日：2013-04-23
申请号：US12893848
申请日：2010-09-29
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K17/162 , H03M1/0845 , H03M1/12 , H03M1/66 , Y10T307/50
摘要： A system includes analog supply circuitry providing first and second analog potentials. A switch module assumes first or second states to enable and inhibit transfer of an analog electrical signal from a source module to a user module based upon a driving electrical signal. A driving device drives, based upon the driving electrical signal, a control terminal of the switch module, allowing the switch module to assume the first or second state. The driving device allows the switch module to make a first driving transition from the first state to the second state, and a second driving transition from the second state to the first state. The driving device alternately connects the control terminal to a first reference potential, during the first state, and to a second reference potential, during the second state. The driving device connects the control terminal of the switch module to a third reference potential electrically distinct from the first and the second analog potentials, during each of the time intervals associated to the first or second driving transitions of the switch module.
摘要翻译： 系统包括提供第一和第二模拟电位的模拟电源电路。 开关模块基于驱动电信号，假设第一或第二状态来启用和禁止模拟电信号从源模块传送到用户模块。 驱动装置基于驱动电信号驱动开关模块的控制端子，允许开关模块呈现第一或第二状态。 驱动装置允许开关模块进行从第一状态到第二状态的第一驱动转变，以及从第二状态到第一状态的第二驱动转变。 在第二状态期间，驱动装置在第一状态期间交替地将控制端子连接到第一参考电位，并将第二参考电位交替地连接到第二参考电位。 在与开关模块的第一或第二驱动转换相关联的每个时间间隔期间，驱动装置将开关模块的控制端子连接到与第一和第二模拟电位电不同的第三参考电位。
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9.发明授权Differential to single-ended conversion circuit and comparator using the circuit 有权差分到单端转换电路和比较器使用电路公开(公告)号：US07888994B2
公开(公告)日：2011-02-15
申请号：US12395409
申请日：2009-02-27
CPC分类号： H03F3/005 , H03F3/45192 , H03F2203/45028 , H03F2203/45138 , H03F2203/45396 , H03F2203/45534 , H03F2203/45726
摘要： An electrical circuit for conversion from differential to single-ended includes a differential amplifier stage and first and second buffer circuits. The differential amplifier stage includes a first and a second input; and a first and a different second charging circuit that can be operatively coupled, respectively, with an output of the conversion circuit and with an auxiliary output. Each of the first and second buffer circuits is functionally arranged between one of said outputs and between one of said charging circuits. The buffer circuits being configured so as to substantially equalize relative impedances seen towards said outputs.
摘要翻译： 用于从差分到单端转换的电路包括差分放大器级和第一和第二缓冲电路。 差分放大器级包括第一和第二输入; 以及可以分别与转换电路的输出和辅助输出可操作地耦合的第一和第二充电电路。 第一和第二缓冲电路中的每一个功能地布置在所述输出之一和所述充电电路之一之间。 缓冲电路被配置为基本上相等于所述输出端所看到的相对阻抗。
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10.发明授权Current steering digital-analog converter particularly insensitive to packaging stresses 有权电流转向数模转换器特别对包装应力不敏感公开(公告)号：US07675449B2
公开(公告)日：2010-03-09
申请号：US12172692
申请日：2008-07-14
IPC分类号： H03M1/66
CPC分类号： H03M1/0648 , H03M1/687 , H03M1/747
摘要： A current steering digital-analog converter for converting a digital code into an analog signal, the converter including a substrate of semiconductor material, an array of current generators integrated in the substrate, a common summation node and switches controllable on the basis of the digital code for connecting and disconnecting the current generators to and from the common summation node. The current generators are adapted to provide the common summation node with currents having a multiple value according to a power of two compared to a unit current value provided to the summation node by a current generator of the array of generators. The current generator is divided into a base number of modular current generation elements in parallel to one another at least equal to two.
摘要翻译： 一种用于将数字代码转换为模拟信号的电流转向数模转换器，所述转换器包括半导体材料的衬底，集成在衬底中的电流发生器的阵列，公共求和节点和基于数字代码可控的开关 用于将当前发生器连接到和从公共求和节点断开连接。 电流发生器适于根据与发电机阵列的电流发生器提供给求和节点的单位电流值相比的功率，为公共求和节点提供具有多个值的电流。 电流发生器被分成基本数量的模块化电流产生元件，彼此平行至少等于2。
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