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    Apparatus and fabrication process to reduce crosstalk in pirm memory array
    1.
    发明授权
    Apparatus and fabrication process to reduce crosstalk in pirm memory array 有权
    设备和制造过程，以减少pirm存储器阵列中的串扰

    公开(公告)号：US06599796B2

    公开(公告)日：2003-07-29

    申请号：US09896480

    申请日：2001-06-29

    申请人： Ping Mei ,  Carl P. Taussig ,  Patricia A. Beck

    发明人： Ping Mei ,  Carl P. Taussig ,  Patricia A. Beck

    IPC分类号： H01L218242

    CPC分类号： H01L27/1021

    摘要： A cross point memory array is fabricated on a substrate with a plurality of memory cells, each memory cell including a diode and an anti-fuse in series. First and second conducting materials are disposed in separate strips on the substrate to form a plurality of first and second orthogonal electrodes with cross points. A plurality of semiconductor layers are disposed between the first and second electrodes to form a plurality of diodes between the cross points of the first and second electrodes. A passivation layer is disposed between the first electrodes and the diodes to form a plurality of anti-fuses adjacent to the diodes at the cross points of first and second electrodes. Portions of the diode layers are removed between the electrode cross points to form the plurality of memory cells with rows of trenches between adjacent memory cells to provide a barrier against crosstalk between adjacent memory cells. The trenches extend substantially to the depth of the n-doped layer in each diode. A process for fabricating the memory array includes formation of the anti-fuse above the diode in each memory cell and extending the passivation material into the trenches as the isolation material. Alternately, the diode may be formed above the anti-fuse, so that the trenches may be substantially more shallow. In addition, a process is provided for fabricating a cross point memory array having a plurality of memory cells on a substrate, each memory cell including a diode adjacent to a line electrode, including etching together in one fabrication step the boundaries extending along a first direction of each of the diodes and each of the line electrodes to form multiple rows of the diodes and the line electrodes extending in the first direction.

    摘要翻译： 在具有多个存储单元的衬底上制造交叉点存储器阵列，每个存储单元包括二极管和串联的反熔丝。 第一和第二导电材料被设置在基板上的分开的条带中以形成具有交叉点的多个第一和第二正交电极。 多个半导体层设置在第一和第二电极之间，以在第一和第二电极的交叉点之间形成多个二极管。 钝化层设置在第一电极和二极管之间，以在第一和第二电极的交叉点处形成与二极管相邻的多个抗熔丝。 二极管层的一部分在电极交叉点之间被去除以形成多个具有在相邻存储器单元之间的行沟槽的存储单元，以提供阻挡相邻存储单元之间串扰的屏障。 沟槽基本上延伸到每个二极管中n掺杂层的深度。 用于制造存储器阵列的工艺包括在每个存储单元中形成二极管上方的反熔丝，并将钝化材料作为隔离材料延伸到沟槽中。 或者，二极管可以形成在反熔丝上方，使得沟槽可以基本上更浅。 此外，提供了一种用于制造在衬底上具有多个存储器单元的交叉点存储器阵列的处理，每个存储单元包括与线电极相邻的二极管，包括在一个制造步骤中一起蚀刻沿着第一方向延伸的边界 的每个二极管和每个线电极以形成多行二极管和沿第一方向延伸的线电极。

    Luminescent Stacked Waveguide Display
    2.
    发明申请
    Luminescent Stacked Waveguide Display 有权
    发光叠层波导显示

    公开(公告)号：US20140233879A1

    公开(公告)日：2014-08-21

    申请号：US14346817

    申请日：2011-10-31

    申请人： Gary Gibson ,  Richard H. Henze ,  Patricia A. Beck ,  Xia Sheng

    发明人： Gary Gibson ,  Richard H. Henze ,  Patricia A. Beck ,  Xia Sheng

    IPC分类号： G02F1/01

    CPC分类号： G02F1/011 ,  G02B6/0003 ,  G02B6/0076 ,  G02F1/1336 ,  G02F1/167 ,  G02F2001/133618

    摘要： A display includes at least two stacked waveguides (110) and (120). A first waveguide (110) contains first luminophores that fluoresce to produce light of a first color. A second waveguide (120) overlying the first waveguide and contains second luminophores that fluoresce to produce light of a second color. A light collection structure (180) transmits light from a surrounding environment transversely through the first and second waveguides (110, 120) and optical vias (172, 174) provide optical paths out of the display for light respectively from the first optical waveguide (110) and the second optical waveguide (120).

    摘要翻译： 显示器包括至少两个堆叠的波导（110）和（120）。 第一波导（110）包含发荧光以产生第一颜色的光的第一发光体。 第二波导（120），其覆盖第一波导并且包含发荧光以产生第二颜色的光的第二发光体。 光收集结构（180）从横向穿过第一和第二波导（110,120）的周围环境透射光，并且光通路（172,174）分别向第一光波导（110） ）和第二光波导（120）。

    Forming an ordered array for visual inspection
    3.
    发明授权
    Forming an ordered array for visual inspection 失效
    形成一个有序的阵列进行目视检查

    公开(公告)号：US4591392A

    公开(公告)日：1986-05-27

    申请号：US680801

    申请日：1984-12-13

    申请人： Patricia A. Beck

    发明人： Patricia A. Beck

    IPC分类号： B08B11/02 ,  G01R31/308 ,  H01L21/302 ,  B08B1/00

    CPC分类号： B08B11/02 ,  G01R31/308 ,  H01L21/302

    摘要： Disclosed is a method of producing a suitable array of semiconductor chips or other objects for visual inspection. Semiconductor chips on the order of a few hundred microns on each side are placed onto a mesh screen in a container, then submersed in deionized water, so that the chips begin to float and the fluid never covers the upper surfaces of the chips. Gently swirling the fluid causes the chips to orient in the center of the container. Continued swirling aligns the chips into an orderly array of rows and columns.

    摘要翻译： 公开了一种生产用于目视检查的半导体芯片或其他物体的合适阵列的方法。 将每侧约数百微米的半导体芯片放置在容器中的筛网上，然后浸入去离子水中，使芯片开始浮起，流体不会覆盖芯片的上表面。 轻轻旋转流体会使芯片在容器的中心定向。 连续旋转将芯片对齐成行和列的有序阵列。

    Method of forming one or more nanopores for aligning molecules for molecular electronics
    5.
    发明授权
    Method of forming one or more nanopores for aligning molecules for molecular electronics 失效
    形成一个或多个用于分子电子学分子的纳米孔的形成方法

    公开(公告)号：US07922927B2

    公开(公告)日：2011-04-12

    申请号：US11906819

    申请日：2007-10-03

    申请人： Theodore I. Kamins ,  Yong Chen ,  Patricia A. Beck

    发明人： Theodore I. Kamins ,  Yong Chen ,  Patricia A. Beck

    IPC分类号： C23F1/00

    CPC分类号： B82Y10/00 ,  B81C1/00031 ,  C03C15/00 ,  C03C17/001 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144

    摘要： A technique is provided for forming a molecule or an array of molecules having a defined orientation relative to the substrate or for forming a mold for deposition of a material therein. The array of molecules is formed by dispersing them in an array of small, aligned holes (nanopores), or mold, in a substrate. Typically, the material in which the nanopores are formed is insulating. The underlying substrate may be either conducting or insulating. For electronic device applications, the substrate is, in general, electrically conducting and may be exposed at the bottom of the pores so that one end of the molecule in the nanopore makes electrical contact to the substrate. A substrate such as a single-crystal silicon wafer is especially convenient because many of the process steps to form the molecular array can use techniques well developed for semiconductor device and integrated-circuit fabrication.

    摘要翻译： 提供了一种用于形成具有相对于基底具有限定取向的分子或分子阵列的技术，或用于形成用于在其中沉积材料的模具。 分子阵列通过将它们分散在基底中的小的，对准的孔（纳米孔）或模具的阵列中而形成。 通常，形成纳米孔的材料是绝缘的。 底层衬底可以是导电的或绝缘的。 对于电子器件应用，基底通常是导电的并且可以在孔的底部暴露，使得纳米孔中的分子的一端与基底电接触。 诸如单晶硅晶片的衬底是特别方便的，因为形成分子阵列的许多工艺步骤可以使用用于半导体器件和集成电路制造的技术。

    Methods of fabricating microneedles with bio-sensory functionality
    6.
    发明申请
    Methods of fabricating microneedles with bio-sensory functionality 审中-公开
    制造具有生物感官功能的微针的方法

    公开(公告)号：US20080097352A1

    公开(公告)日：2008-04-24

    申请号：US11520526

    申请日：2006-09-12

    申请人： Patricia A. Beck ,  Ramesh Govinda Raju ,  Xio-An Sean Zhang

    发明人： Patricia A. Beck ,  Ramesh Govinda Raju ,  Xio-An Sean Zhang

    IPC分类号： A61M5/32

    CPC分类号： B81C1/00111 ,  A61B5/14542 ,  A61B5/1473 ,  A61B5/685 ,  A61M37/0015 ,  B81B2201/055 ,  B81C2201/0197 ,  Y10T29/49204

    摘要： A method of fabricating a microneedle is disclosed. The method includes forming at least one recess in a substrate, the at least one recess comprising an apex, forming an electrically seed layer on the substrate including the at least one recess, forming at least one electrically nonconductive pattern on a portion of the seed layer, the at least one nonconductive pattern being a pattern for a sensory area, plating an electrically conductive material on the seed layer to create a plated layer with an opening that exposes a portion of the nonconductive pattern and separating the plated layer from the seed layer and the at least one nonconductive pattern to release a hollow microneedle comprising a tip and at least one sensory area.

    摘要翻译： 公开了一种制造微针的方法。 该方法包括在衬底中形成至少一个凹部，所述至少一个凹部包括顶点，在衬底上形成包括所述至少一个凹部的电晶种层，在种子层的一部分上形成至少一个非导电图案 所述至少一个非导电图案是用于感觉区域的图案，在所述种子层上镀覆导电材料以产生具有暴露所述非导电图案的一部分并将所述镀层与所述种子层分离的开口的镀层，以及 所述至少一个非导电图案以释放包括尖端和至少一个感觉区域的中空微针。

    Batch fabricated molecular electronic devices with cost-effective lithographic electrodes
    10.
    发明授权
    Batch fabricated molecular electronic devices with cost-effective lithographic electrodes 失效
    批量制造具有成本效益的平版印刷电极的分子电子器件

    公开(公告)号：US06458621B1

    公开(公告)日：2002-10-01

    申请号：US09920994

    申请日：2001-08-01

    申请人： Patricia A. Beck

    发明人： Patricia A. Beck

    IPC分类号： H01L2100

    CPC分类号： G11C13/0014 ,  B82Y10/00 ,  G11C13/02 ,  G11C2213/77

    摘要： An improved method of fabricating nanometer-scale devices is provided, wherein the improvement comprises: (1) employing materials for a first electrode, a first insulating layer, if present, a molecular switch layer, a second insulating layer, if present, and a second electrode that permit photopatterning of the second electrode; and (2) photopatterning at least the second electrode without adversely affecting the molecular switch layer. The improved method incorporates known techniques on a smaller scale than previously done to provide a means to move away from shadow mask electrodes (many micrometers wide), presently used in nanometer-scale devices, and move to nanometer dimensions. The improved method further facilitates integration of nanometer-scale devices to larger silicon-based technology.

    摘要翻译： 提供了一种制造纳米级器件的改进方法，其中改进包括：（1）使用材料用于第一电极，第一绝缘层（如果存在），分子开关层，第二绝缘层（如果存在）和 允许第二电极的光图案化的第二电极; 和（2）至少对第二电极进行光图案化，而不会对分子开关层产生不利影响。 改进的方法结合了比以前更小规模的已知技术，以提供一种移动远离目前用于纳米级装置的荫罩电极（许多微米宽）并移动到纳米尺寸的手段。 该改进的方法进一步有助于将纳米级器件集成到更大的基于硅的技术。