公开(公告)号：US07922927B2

公开(公告)日：2011-04-12

申请号：US11906819

申请日：2007-10-03

申请人： Theodore I. Kamins ,  Yong Chen ,  Patricia A. Beck

发明人： Theodore I. Kamins ,  Yong Chen ,  Patricia A. Beck

IPC分类号： C23F1/00

CPC分类号： B82Y10/00 ,  B81C1/00031 ,  C03C15/00 ,  C03C17/001 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144

摘要： A technique is provided for forming a molecule or an array of molecules having a defined orientation relative to the substrate or for forming a mold for deposition of a material therein. The array of molecules is formed by dispersing them in an array of small, aligned holes (nanopores), or mold, in a substrate. Typically, the material in which the nanopores are formed is insulating. The underlying substrate may be either conducting or insulating. For electronic device applications, the substrate is, in general, electrically conducting and may be exposed at the bottom of the pores so that one end of the molecule in the nanopore makes electrical contact to the substrate. A substrate such as a single-crystal silicon wafer is especially convenient because many of the process steps to form the molecular array can use techniques well developed for semiconductor device and integrated-circuit fabrication.

摘要翻译： 提供了一种用于形成具有相对于基底具有限定取向的分子或分子阵列的技术，或用于形成用于在其中沉积材料的模具。 分子阵列通过将它们分散在基底中的小的，对准的孔（纳米孔）或模具的阵列中而形成。 通常，形成纳米孔的材料是绝缘的。 底层衬底可以是导电的或绝缘的。 对于电子器件应用，基底通常是导电的并且可以在孔的底部暴露，使得纳米孔中的分子的一端与基底电接触。 诸如单晶硅晶片的衬底是特别方便的，因为形成分子阵列的许多工艺步骤可以使用用于半导体器件和集成电路制造的技术。

公开(公告)号：US20080203055A1

公开(公告)日：2008-08-28

申请号：US11906819

申请日：2007-10-03

申请人： Theodore I. Kamins ,  Yong Chen ,  Patricia A. Beck

发明人： Theodore I. Kamins ,  Yong Chen ,  Patricia A. Beck

IPC分类号： B31D3/00

CPC分类号： B82Y10/00 ,  B81C1/00031 ,  C03C15/00 ,  C03C17/001 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144

摘要： A technique is provided for forming a molecule or an array of molecules having a defined orientation relative to the substrate or for forming a mold for deposition of a material therein. The array of molecules is formed by dispersing them in an array of small, aligned holes (nanopores), or mold, in a substrate. Typically, the material in which the nanopores are formed is insulating. The underlying substrate may be either conducting or insulating. For electronic device applications, the substrate is, in general, electrically conducting and may be exposed at the bottom of the pores so that one end of the molecule in the nanopore makes electrical contact to the substrate. A substrate such as a single-crystal silicon wafer is especially convenient because many of the process steps to form the molecular array can use techniques well developed for semiconductor device and integrated-circuit fabrication.

摘要翻译： 提供了一种用于形成具有相对于基底具有限定取向的分子或分子阵列的技术，或用于形成用于在其中沉积材料的模具。 分子阵列通过将它们分散在基底中的小的，对准的孔（纳米孔）或模具的阵列中而形成。 通常，形成纳米孔的材料是绝缘的。 底层衬底可以是导电的或绝缘的。 对于电子器件应用，基底通常是导电的并且可以在孔的底部暴露，使得纳米孔中的分子的一端与基底电接触。 诸如单晶硅晶片的衬底是特别方便的，因为形成分子阵列的许多工艺步骤可以使用用于半导体器件和集成电路制造的技术。

公开(公告)号：US07378347B2

公开(公告)日：2008-05-27

申请号：US10281678

申请日：2002-10-28

申请人： Theodore I. Kamins ,  Philip J. Kuekes ,  Yong Chen

发明人： Theodore I. Kamins ,  Philip J. Kuekes ,  Yong Chen

IPC分类号： H01L21/461

CPC分类号： B82Y30/00 ,  B82Y10/00 ,  C30B11/00 ,  C30B11/12 ,  C30B29/605 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods for forming a predetermined pattern of catalytic regions having nanoscale dimensions are provided for use in the growth of nanowires. The methods include one or more nanoimprinting steps to produce arrays of catalytic nanoislands or nanoscale regions of catalytic material circumscribed by noncatalytic material.

摘要翻译： 提供用于形成具有纳米级尺寸的催化区域的预定图案的方法用于纳米线的生长。 所述方法包括一个或多个纳米压印步骤，以产生由非催化材料限定的催化材料的催化纳米级或纳米尺度区域的阵列。

公开(公告)号：US06773616B1

公开(公告)日：2004-08-10

申请号：US10033408

申请日：2001-12-26

申请人： Yong Chen ,  Douglas A. A. Ohlberg ,  Theodore I. Kamins ,  R. Stanley Williams

发明人： Yong Chen ,  Douglas A. A. Ohlberg ,  Theodore I. Kamins ,  R. Stanley Williams

IPC分类号： B44C122

CPC分类号： C30B23/02 ,  C30B25/02 ,  C30B29/605 ,  Y10S977/888

摘要： Self-organized, or self-assembled, nanowires of a first composition may be used as an etching mask for fabrication of nanowires of a second composition. The method for forming such nanowires comprises: (a) providing an etchable layer of the second composition and having a buried insulating layer beneath a major surface thereof; (b) growing self-assembled nanowires on the surface of the etchable layer; and (c) etching the etchable layer anisotropically down to the insulating layer, using the self-assembled nanowires as a mask. The self-assembled nanowires may be removed or left. In either event, nanowires of the second composition are formed. The method enables the formation of one-dimensional crystalline nanowires with widths and heights at the nanometer scale, and lengths at the micrometer scale, which are aligned along certain crystallographic directions with high crystal quality. Further, the method of the present invention avoids traditional lithography methods, minimizes environmental toxic chemicals usage, simplifies the manufacturing processes, and allows the formation of high-quality one-dimensional nanowires over large areas.

摘要翻译： 可以将第一组合物的自组织或自组装的纳米线用作用于制造第二组合物的纳米线的蚀刻掩模。 形成这种纳米线的方法包括：（a）提供第二组合物的可蚀刻层，并在其主表面下方具有掩埋绝缘层; （b）在可蚀刻层的表面上生长自组装纳米线; 和（c）使用自组装纳米线作为掩模，各向异性地将可蚀刻层蚀刻到绝缘层。 自组装纳米线可以被去除或留下。 在任一情况下，形成第二组合物的纳米线。 该方法能够形成具有纳米尺度的宽度和高度的一维结晶纳米线，以及在具有高晶体质量的某些晶体方向上对准的微米尺度的长度。 此外，本发明的方法避免了传统的光刻方法，使环境有毒化学品的使用最小化，简化了制造工艺，并且允许在大面积上形成高质量的一维纳米线。

公开(公告)号：US06211095B1

公开(公告)日：2001-04-03

申请号：US09221025

申请日：1998-12-23

申请人： Yong Chen ,  Scott W. Corzine ,  Theodore I. Kamins ,  Michael J. Ludowise ,  Pierre H. Mertz ,  Shih-Yuan Wang

发明人： Yong Chen ,  Scott W. Corzine ,  Theodore I. Kamins ,  Michael J. Ludowise ,  Pierre H. Mertz ,  Shih-Yuan Wang

IPC分类号： H01L2131

CPC分类号： H01L21/7624 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02538 ,  H01L21/0254 ,  H01L21/02658 ,  H01L21/26533

摘要： A method for growing a crystalline layer that includes a first material on a growth surface of a crystalline substrate of a second material, wherein the first material and the second material have different lattice constants. A buried layer is generated in the substrate such that the buried layer isolates a layer of the substrate that includes the growth surface from the remainder of the substrate. The first material is then deposited on the growth surface at a growth temperature. The isolated layer of the substrate has a thickness that is less than the thickness at which defects are caused in the crystalline lattice of the second material by the first material crystallizing thereon. The buried layer is sufficiently malleable at the growth temperature to allow the deformation of the lattice of the isolated layer without deforming the remainder of the substrate. The present invention may be utilized for growing III-V semiconducting material layers on silicon substrates. In the case of silicon-based substrates, the buried layer is preferably SiO2 that is sufficiently malleable at the growth temperature to allow the deformation of the isolated substrate layer.

摘要翻译： 一种用于生长晶体层的方法，其包括在第二材料的晶体衬底的生长表面上的第一材料，其中第一材料和第二材料具有不同的晶格常数。 在衬底中产生掩埋层，使得掩埋层将衬底的包含生长表面的衬底与衬底的其余部分隔离。 然后在生长温度下将第一种材料沉积在生长表面上。 衬底的隔离层的厚度小于通过第一材料在其上结晶而在第二材料的晶格中引起缺陷的厚度。 掩埋层在生长温度下具有足够的延展性，以允许隔离层的晶格变形，而不使基底的其余部分变形。 本发明可用于在硅衬底上生长III-V半导体材料层。 在硅基基板的情况下，掩埋层优选是在生长温度下足够有韧性的SiO 2，以允许隔离的基底层的变形。

公开(公告)号：US20080296785A1

公开(公告)日：2008-12-04

申请号：US12150063

申请日：2008-04-23

申请人： Theodore I. Kamins ,  Philip J. Kuekes ,  Yong Chen

发明人： Theodore I. Kamins ,  Philip J. Kuekes ,  Yong Chen

IPC分类号： H01L23/48

CPC分类号： B82Y30/00 ,  B82Y10/00 ,  C30B11/00 ,  C30B11/12 ,  C30B29/605 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods for forming a predetermined pattern of catalytic regions having nanoscale dimensions are provided for use in the growth of nanowires. The methods include one or more nanoimprinting steps to produce arrays of catalytic nanoislands or nanoscale regions of catalytic material circumscribed by noncatalytic material.

公开(公告)号：US06429466B2

公开(公告)日：2002-08-06

申请号：US09774199

申请日：2001-01-29

申请人： Yong Chen ,  Scott W. Corzine ,  Theodore I. Kamins ,  Michael J. Ludowise ,  Pierre H. Mertz ,  Shih-Yuan Wang

发明人： Yong Chen ,  Scott W. Corzine ,  Theodore I. Kamins ,  Michael J. Ludowise ,  Pierre H. Mertz ,  Shih-Yuan Wang

IPC分类号： H01L31072

CPC分类号： H01L21/7624 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02538 ,  H01L21/0254 ,  H01L21/02658 ,  H01L21/26533

摘要： A method for growing a crystalline layer that includes a first material on a growth surface of a crystalline substrate of a second material, wherein the first material and the second material have different lattice constants. A buried layer is generated in the substrate such that the buried layer isolates a layer of the substrate that includes the growth surface from the remainder of the substrate. The second material is then deposited on the growth surface at a growth temperature. The isolated layer of the substrate has a thickness that is less than the thickness at which defects are caused in the crystalline lattice of the first material by the second material crystallizing thereon. The buried layer is sufficiently malleable at the growth temperature to allow the deformation of the lattice of the isolated layer without deforming the remainder of the substrate. The present invention may be utilized for growing III-V semiconducting material layers on silicon substrates. In the case of silicon-based substrates, the buried layer is preferably SiO2 that is sufficiently malleable at the growth temperature to allow the deformation of the isolated substrate layer.

摘要翻译： 一种用于生长晶体层的方法，其包括在第二材料的晶体衬底的生长表面上的第一材料，其中第一材料和第二材料具有不同的晶格常数。 在衬底中产生掩埋层，使得掩埋层将衬底的包含生长表面的衬底与衬底的其余部分隔离。 然后将第二种材料在生长温度下沉积在生长表面上。 衬底的隔离层的厚度小于在其上结晶第二材料时在第一材料的晶格中产生缺陷的厚度。 掩埋层在生长温度下具有足够的延展性，以允许隔离层的晶格变形，而不使基底的其余部分变形。 本发明可用于在硅衬底上生长III-V半导体材料层。 在硅基基板的情况下，掩埋层优选是在生长温度下足够有韧性的SiO 2，以允许隔离的基底层的变形。

公开(公告)号：US08787064B2

公开(公告)日：2014-07-22

申请号：US13130805

申请日：2009-01-13

申请人： Theodore I. Kamins ,  R. Stanley Williams

发明人： Theodore I. Kamins ,  R. Stanley Williams

IPC分类号： G11C11/00

CPC分类号： G11C13/0002 ,  G11C13/003 ,  G11C2213/52 ,  G11C2213/53 ,  H01L27/101 ,  H01L27/1026 ,  H01L45/08 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/14 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147

摘要： A configurable memristive device (300) for regulating an electrical signal includes a memristive matrix (350) containing a first dopant species; emitter (320), collector (310), and a base electrodes (330, 340) which are in contact with the memristive matrix (350); and a mobile dopant species contained within a central region (360) contiguous with the base electrodes (330, 340), the mobile dopant species moving within the memristive matrix (350) in response to a programming electrical field. A method of configuring and using a memristive device (300) includes: applying a programming electrical field across a memristive matrix (350) such that a mobile dopant species creates a central doped region (360) which bisects the memristive matrix (350); and applying a control voltage to the central doped region (360) to regulate current flow between an emitter electrode (320) and a collector electrode (310).

摘要翻译： 用于调节电信号的可配置忆阻装置（300）包括含有第一掺杂剂物质的忆阻矩阵（350） 发射极（320），集电极（310）以及与所述忆阻矩阵（350）接触的基极（330,340）; 以及包含在与所述基极（330,340）相邻的中心区域（360）内的移动掺杂剂物质，所述移动掺杂剂物质响应于编程电场在所述忆阻矩阵（350）内移动。 一种配置和使用忆阻器件（300）的方法包括：跨越忆阻矩阵（350）施加编程电场，使得移动掺杂物物质形成将所述忆阻矩阵（350）平分的中心掺杂区域（360）; 以及向所述中心掺杂区域（360）施加控制电压以调节发射极电极（320）和集电极电极（310）之间的电流。

公开(公告)号：US08569900B2

公开(公告)日：2013-10-29

申请号：US13383183

申请日：2009-07-20

申请人： Nathaniel J. Quitoriano ,  Theodore I. Kamins ,  Hans S. Cho

发明人： Nathaniel J. Quitoriano ,  Theodore I. Kamins ,  Hans S. Cho

IPC分类号： H01L23/58

CPC分类号： B81B1/00 ,  B81B2201/0214

摘要： A nanowire device includes a nanowire having differently functionalized segments. Each of the segments is configured to interact with a species to modulate the conductance of a segment. The nanowire is grown from a single catalyst and the segments include a first segment at a non-linear angle from a second segment.

摘要翻译： 纳米线器件包括具有不同功能化片段的纳米线。 每个片段被配置为与物种相互作用以调节片段的电导。 纳米线从单个催化剂生长，并且所述段包括与第二段非线性角度的第一段。

公开(公告)号：US08223331B2

公开(公告)日：2012-07-17

申请号：US12487940

申请日：2009-06-19

申请人： Alexandre M. Bratkovski ,  Theodore I. Kamins

发明人： Alexandre M. Bratkovski ,  Theodore I. Kamins

IPC分类号： G01J3/44

CPC分类号： G01N21/658

摘要： A signal-amplification device for surface enhanced Raman spectroscopy (SERS). The signal-amplification device includes a non-SERS-active (NSA) substrate, a plurality of multi-tiered non-SERS-active nanowire (MNSANW) structures and a plurality of metallic SERS-active nanoparticles. In addition, a MNSANW structure of the plurality of MNSANW structures includes a main arm of a plurality of main arms and a plurality of arms of at least secondary order. The plurality of main arms is disposed on the NSA substrate; and, a secondary arm of the plurality of arms is disposed on the main arm. Moreover, a metallic SERS-active nanoparticle of the plurality of metallic SERS-active nanoparticles is disposed on a surface of the MNSANW structure.

摘要翻译： 用于表面增强拉曼光谱（SERS）的信号放大装置。 信号放大装置包括非SERS活性（NSA）衬底，多个多层非SERS活性纳米线（MNSANW）结构和多个金属SERS活性纳米颗粒。 此外，多个MNSANW结构的MNSANW结构包括多个主臂的主臂和至少二次的多个臂。 多个主臂设置在NSA基板上; 并且所述多个臂的次臂设置在所述主臂上。 此外，多个金属SERS活性纳米颗粒的金属SERS活性纳米颗粒设置在MNSANW结构的表面上。