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1.发明授权
公开(公告)号：US5924119A
公开(公告)日：1999-07-13
申请号：US188660
申请日：1994-01-27
IPC分类号： G06F13/42 , G06F12/08 , G06F13/364 , G06F12/00
CPC分类号： G06F13/364 , G06F12/0831
摘要： A shared memory multiprocessor having a packet switched bus for transferring data between a plurality processors, I/O devices, cache memories and main memory employs a bus protocol which permits multiple copies of data to be updated under the control of different processors while still ensuring that all processors and all I/O devices have access to consistent values for all data at all times.
摘要翻译： 具有用于在多个处理器，I / O设备，高速缓冲存储器和主存储器之间传送数据的分组交换总线的共享存储器多处理器采用允许在不同处理器的控制下更新数据的多个副本的总线协议，同时仍然确保 所有处理器和所有I / O设备始终可以访问所有数据的一致值。
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2.发明授权Arbitration of packet switched busses, including busses for shared memory multiprocessors 失效分组交换总线的仲裁，包括共享内存多处理器的总线
公开(公告)号：US5440698A
公开(公告)日：1995-08-08
申请号：US236883
申请日：1994-04-29
IPC分类号： G06F12/08 , G06F13/362 , G06F13/364 , G06F15/16 , G06F15/177 , G06F13/14 , G06F13/16 , G06F13/36 , G06F13/42
CPC分类号： G06F13/364
摘要： An arbiter is provided for resolving contention on synchronous packet switched busses, including busses composed of a plurality of pipelined segments, to ensure that all devices serviced by such a bus are given fair, bounded time access to the bus and to permit such devices to fill all available bus cycles with packets. Flow control for shared memory multiprocessors is readily implemented with this arbiter because the arbiter supports different types of arbitration requests and the prioritization of such arbitration requests by type.
摘要翻译： 提供了一种仲裁器，用于解决同步分组交换总线上的竞争，包括由多个流水线段组成的总线，以确保由这样的总线服务的所有设备被给予公平的有限时间的访问总线并且允许这样的设备填充 所有可用的总线周期与数据包。 共享存储器多处理器的流控制可以很容易地用这个仲裁器来实现，因为仲裁器支持不同类型的仲裁请求以及类型的这种仲裁请求的优先级。
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3.发明授权
公开(公告)号：US5195089A
公开(公告)日：1993-03-16
申请号：US636446
申请日：1990-12-31
申请人： Pradeep S. Sindhu , Bjorn Liencres , Jorge Cruz-Rios , Douglas B. Lee , Jung-Herng Chang , Jean-Marc Frailong
发明人： Pradeep S. Sindhu , Bjorn Liencres , Jorge Cruz-Rios , Douglas B. Lee , Jung-Herng Chang , Jean-Marc Frailong
IPC分类号： G06F13/36 , G06F12/08 , G06F12/10 , G06F13/362 , G06F13/364 , G06F13/38 , G06F15/16
CPC分类号： G06F12/0831 , G06F12/1027 , G06F13/364 , G06F2212/682
摘要： A high speed, synchronous, packet-switched inter-chip bus apparatus and method for transferring data between multiple system buses and a cache controller. In the preferred embodiment, the bus connects a cache controller client within the external cache of a processor to a plurality of bus watcher clients, each of which is coupled to a separate system bus. The bus allows the cache controller to provide independent processor-side access to the cache and allows the bus watchers to handle functions related to bus-snooping. An arbiter is employed to allow the bus to be multiplexed between the bus watchers and cache controller. Flow control mechanisms are also employed to ensure that queues receiving packets or arbitration requests over the bus never overflow. A default grantee mechanism is employed to minimize the arbitration latency due to a request for the bus when the bus is idle.
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4.发明授权公开(公告)号：US06175650B1
公开(公告)日：2001-01-16
申请号：US09013480
申请日：1998-01-26
IPC分类号： G06K900
CPC分类号： G06T9/005
摘要： Pixel blocks of an input image are type classified based on an analysis of the secord differences between the values of neighboring pixels in the rows and columns of each pixel block. A histogram of these second order differences may be employed to refine this analysis
摘要翻译： 基于对每个像素块的行和列中的相邻像素的值之间的秒差的分析，输入图像的像素块是类型分类的。 可以使用这些二阶差分的直方图来改进该分析
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公开(公告)号：US09847953B2
公开(公告)日：2017-12-19
申请号：US12495364
申请日：2009-06-30
IPC分类号： H04L12/28 , H04L12/931 , H04L12/933 , H04L12/947
CPC分类号： H04L49/35 , H04L49/00 , H04L49/1515 , H04L49/251 , H04L49/356 , H04L49/70
摘要： In one embodiment, an apparatus includes a switch core that has a multi-stage switch fabric. A first set of peripheral processing devices coupled to the multi-stage switch fabric by a set of connections that have a protocol. Each peripheral processing device from the first set of peripheral processing devices is a storage node that has virtualized resources. The virtualized resources of the first set of peripheral processing devices collectively define a virtual storage resource interconnected by the switch core. A second set of peripheral processing devices coupled to the multi-stage switch fabric by a set of connections that have the protocol. Each peripheral processing device from the first set of peripheral processing devices is a compute node that has virtualized resources. The virtualized resources of the second set of peripheral processing devices collectively define a virtual compute resource interconnected by the switch core.
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公开(公告)号：US08938469B1
公开(公告)日：2015-01-20
申请号：US13239774
申请日：2011-09-22
申请人： John Keen , Jean-Marc Frailong , Deepak Goel
发明人： John Keen , Jean-Marc Frailong , Deepak Goel
IPC分类号： G06F17/30
CPC分类号： H04L45/7453
摘要： An example hashing unit includes a plurality of hardware-based hash tables, wherein each of the hash tables comprises a plurality of buckets, and wherein the plurality of hash tables comprise a set of zero or more active hash tables and a set of one or more inactive hash tables. An example hashing unit controller is configured to receive a key value to be stored in the hashing unit, determine that one of the inactive hash tables should be activated, and, based on the determination, activate the one of the set of inactive hash tables as a recently activated hash table, determine one of the buckets of the recently activated hash table to which a hash function associated with the recently activated hash table maps the received key value, and store the key value in the determined one of the buckets of the recently activated hash table.
摘要翻译： 示例性散列单元包括多个基于硬件的散列表，其中每个散列表包括多个桶，并且其中所述多个散列表包括一组零个或多个活动散列表和一组一个或多个 不活动的哈希表。 示例性散列单元控制器被配置为接收要存储在散列单元中的密钥值，确定应激活其中一个非活动散列表，并且基于该确定，将该非活动散列表中的一个激活为 最近激活的散列表确定最近激活的散列表的一个桶，其中与最近激活的散列表相关联的散列函数映射到接收到的密钥值，并将密钥值存储在最近确定的一个桶中 激活哈希表。
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公开(公告)号：US08798045B1
公开(公告)日：2014-08-05
申请号：US12345498
申请日：2008-12-29
申请人： Gunes Aybay , Jean-Marc Frailong
发明人： Gunes Aybay , Jean-Marc Frailong
CPC分类号： H04L41/12 , H04L49/10 , H04L49/25 , H04L49/357 , H04Q11/0001 , H04Q11/0005 , H04Q11/0066 , H04Q2011/0039 , H04Q2011/0052 , H04Q2011/009
摘要： In some embodiments, a system includes multiple access switches, a switch fabric having multiple switch fabric portions, and a control plane processor. Each switch fabric portion is coupled to at least one access switch by a cable from a first set of cables. Each switch fabric portion is configured to receive data from the at least one access switch via the cable from the first set of cables. The control plane processor is coupled to each switch fabric portion by a cable from a second set of cables. The control plane processor is configured to send control information to each access switch via a cable from the second set of cables, a switch fabric portion, and a cable from the first set of cables. The control plane processor is configured to determine control plane connections associated with each access switch and is configured to determine data plane connections associated with each access switch as a result of the control plane connections.
摘要翻译： 在一些实施例中，系统包括多个接入交换机，具有多个交换结构部分的交换机结构以及控制平面处理器。 每个交换结构部分通过来自第一组电缆的电缆耦合到至少一个接入交换机。 每个交换结构部分被配置为经由来自第一组电缆的电缆从至少一个接入交换机接收数据。 控制平面处理器通过来自第二组电缆的电缆耦合到每个交换结构部分。 控制平面处理器被配置为经由来自第二组电缆的电缆，交换结构部分和来自第一组电缆的电缆向每个接入交换机发送控制信息。 控制平面处理器被配置为确定与每个接入交换机相关联的控制平面连接，并且被配置为由于控制平面连接而确定与每个接入交换机相关联的数据平面连接。
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8.发明授权Methods and apparatus for defining a flow control signal related to a transmit queue 有权用于定义与发送队列相关的流控制信号的方法和装置公开(公告)号：US08593970B2
公开(公告)日：2013-11-26
申请号：US13541080
申请日：2012-07-03
申请人： Avanindra Godbole , Arghajit Basu , Jean-Marc Frailong , Abhijeet Sampatrao Jadav , Naveen Jain , Pradeep Sindhu
发明人： Avanindra Godbole , Arghajit Basu , Jean-Marc Frailong , Abhijeet Sampatrao Jadav , Naveen Jain , Pradeep Sindhu
IPC分类号： H04L1/00
CPC分类号： H04L49/9078 , H04L47/12 , H04L47/26 , H04L47/30 , H04L47/52
摘要： In one embodiment, a processor-readable medium can store code representing instructions that when executed by a processor cause the processor to receive a value representing a congestion level of a receive queue and a value representing a state of a transmit queue. At least a portion of the transmit queue can be defined by a plurality of packets addressed to the receive queue. A rate value for the transmit queue can be defined based on the value representing the congestion level of the receive queue and the value representing the state of the transmit queue. The processor-readable medium can store code representing instructions that when executed by the processor cause the processor to define a suspension time value for the transmit queue based on the value representing the congestion level of the receive queue and the value representing the state of the transmit queue.
摘要翻译： 在一个实施例中，处理器可读介质可以存储表示当由处理器执行时指示处理器接收表示接收队列的拥塞级别的值的代码和表示发送队列的状态的值的代码。 发送队列的至少一部分可以由寻址到接收队列的多个分组来定义。 可以基于表示接收队列的拥塞级别的值和表示发送队列状态的值来定义传输队列的速率值。 处理器可读介质可以存储表示指令的代码，当处理器执行时，该处理器使得处理器基于表示接收队列的拥塞级别的值和发送的状态的值来定义发送队列的暂停时间值 队列。
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公开(公告)号：US08498306B2
公开(公告)日：2013-07-30
申请号：US13045312
申请日：2011-03-10
IPC分类号： H04L12/56
CPC分类号： H04L49/552 , H04L49/90 , H04L49/9047 , H04L49/9094
摘要： Data units received by a network device may be classified into traffic flow classes in which the determined traffic flow class for a data unit may be dynamically refined as the data unit is processed by the network device. A dispatch component of the network device may receive data units associated with traffic flow classes. Parallel processing engines of the network device may receive the data units from the dispatch component and may generate, for a least one of the data units, a plurality of dynamically refined indications of the traffic flow class to which the data unit belongs. Additionally, an ordering component of the network device may include a plurality of re-order queues, where the at least one data unit successively progresses through at least two of the re-order queues in an order defined by the plurality of dynamically refined indications of the traffic flow class.
摘要翻译： 由网络设备接收的数据单元可以被分类为业务流类别，其中所确定的数据单元的业务流类别可以由网络设备处理数据单元时动态地改进。 网络设备的调度组件可以接收与业务流类别相关联的数据单元。 网络设备的并行处理引擎可以从调度组件接收数据单元，并且可以为数据单元中的至少一个数据单元生成数据单元所属的业务流类别的多个动态精确的指示。 另外，网络设备的排序组件可以包括多个重新排序队列，其中至少一个数据单元以由多个动态精简指示定义的顺序连续地进行至少两个重排队列 交通流量类。
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10.发明授权Methods and apparatus for transmission of groups of cells via a switch fabric 有权用于经由交换结构传输小区组的方法和装置公开(公告)号：US08325749B2
公开(公告)日：2012-12-04
申请号：US12343728
申请日：2008-12-24
申请人： Sarin Thomas , Srihari Vegesna , Pradeep Sindhu , Chi-Chung Kenny Chen , Jean-Marc Frailong , David J. Ofelt , Philip A. Thomas , Chang-Hong Wu
发明人： Sarin Thomas , Srihari Vegesna , Pradeep Sindhu , Chi-Chung Kenny Chen , Jean-Marc Frailong , David J. Ofelt , Philip A. Thomas , Chang-Hong Wu
IPC分类号： H04L12/28
CPC分类号： H04J3/00 , H04L49/251 , H04L49/254
摘要： In one embodiment, a method can include receiving at an egress schedule module a request to schedule transmission of a group of cells from an ingress queue through a switch fabric of a multi-stage switch. The ingress queue can be associated with an ingress stage of the multi-stage switch. The egress schedule module can be associated with an egress stage of the multi-stage switch. The method can also include determining, in response to the request, that an egress port at the egress stage of the multi-stage switch is available to transmit the group of cells from the multi-stage switch.
摘要翻译： 在一个实施例中，一种方法可以包括在出口调度模块处接收通过多级交换机的交换结构调度来自进入队列的小区的传输的请求。 入站队列可以与多级交换机的进入级相关联。 出口调度模块可以与多级交换机的出口级相关联。 该方法还可以包括响应于该请求确定多级交换机的出口级的出口端口可用于从多级交换机发送小区组。
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