公开(公告)号：US20140252409A1

公开(公告)日：2014-09-11

申请号：US13794038

申请日：2013-03-11

申请人： Gary H. Loechelt ,  Carroll Casteel

发明人： Gary H. Loechelt ,  Carroll Casteel

IPC分类号： H01L27/06

CPC分类号： H01L27/0629 ,  H02M1/32 ,  H02M3/1588 ,  H02M7/538 ,  H03K17/0814 ,  H03K17/162 ,  H03K17/74

摘要： A circuit can include a pair of switching elements that have terminals electrically connected to terminals of a power supply and have other terminals electrically connected to an output terminal. The circuit can include rectifying elements and one or more charge storage elements. The circuit may be used as a Buck converter. The rectifying element(s) and charge storage element(s) may help to reduce ringing at an output terminal of the circuit during normal operation and reduce the likelihood of exceeding a breakdown voltage between current-carrying electrodes of a switching element within the circuit during a switching operation.

摘要翻译： 电路可以包括一对开关元件，其具有电连接到电源的端子的端子，并且其他端子电连接到输出端子。 电路可以包括整流元件和一个或多个电荷存储元件。 该电路可以用作降压转换器。 整流元件和电荷存储元件可以有助于在正常操作期间减少电路的输出端子处的振铃，并且减小在电路内的开关元件的载流电极之间的击穿电压的可能性 切换操作。

公开(公告)号：US20130153988A1

公开(公告)日：2013-06-20

申请号：US13327454

申请日：2011-12-15

申请人： Gary H. Loechelt ,  Gordon M. Grivna

发明人： Gary H. Loechelt ,  Gordon M. Grivna

IPC分类号： H01L29/78 ,  H01L21/308

CPC分类号： H01L21/3086 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/743 ,  H01L29/401 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66659 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/7816 ,  H01L29/7835

摘要： An electronic device can include a transistor structure including a semiconductor layer overlying a substrate and a trench extending into the semiconductor layer having a tapered shape. In an embodiment, the tapered shape includes a facet. The transistor structure can include a source region and a drain region wherein different portions of the drain regions are disposed adjacent to the primary surface and within the trench. In another embodiment, different facets may be spaced apart from each other. Processes of forming the tapered etch can be tailored based on the needs or desires of a fabricator.

摘要翻译： 电子器件可以包括晶体管结构，其包括覆盖衬底的半导体层和延伸到具有锥形形状的半导体层的沟槽。 在一个实施例中，锥形形状包括小面。 晶体管结构可以包括源极区域和漏极区域，其中漏极区域的不同部分邻近主要表面设置并且在沟槽内。 在另一个实施例中，不同的刻面可以彼此间隔开。 可以根据制造商的需要或期望来定制形成锥形蚀刻的工艺。

公开(公告)号：US20110193160A1

公开(公告)日：2011-08-11

申请号：US12702055

申请日：2010-02-08

申请人： Gary H. Loechelt ,  Gordon M. Grivna ,  Peter J. Zdebel

发明人： Gary H. Loechelt ,  Gordon M. Grivna ,  Peter J. Zdebel

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L29/66696 ,  H01L21/26586 ,  H01L21/2815 ,  H01L21/743 ,  H01L21/823475 ,  H01L27/1203 ,  H01L29/0626 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1008 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/42376 ,  H01L29/6625 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/735 ,  H01L29/7824 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electronic device can include a buried conductive region, a buried insulating layer over the buried conductive region, and a semiconductor layer disposed over the buried insulating layer, wherein the semiconductor layer has a primary surface and an opposing surface, and the buried conductive region is disposed closer to the opposing surface than to the primary surface. The electronic device can also include a current-carrying electrode of a first transistor, wherein the current carrying electrode is disposed along the primary surface and spaced apart from the buried conductive layer. The electronic device can also include a vertical conductive structure extending through the buried insulating layer, wherein the vertical conductive structure is electrically connected to the current-carrying electrode and the buried conductive region.

摘要翻译： 电子器件可以包括掩埋导电区域，掩埋导电区域上的掩埋绝缘层和设置在掩埋绝缘层上的半导体层，其中半导体层具有主表面和相对表面，并且掩埋导电区域 相对于主表面更靠近对置的表面。 电子设备还可以包括第一晶体管的载流电极，其中载流电极沿着主表面设置并与掩埋的导电层间隔开。 电子器件还可以包括延伸穿过掩埋绝缘层的垂直导电结构，其中垂直导电结构电连接到载流电极和掩埋导电区域。

公开(公告)号：US20110068344A1

公开(公告)日：2011-03-24

申请号：US12958002

申请日：2010-12-01

申请人： Gary H. Loechelt

发明人： Gary H. Loechelt

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L21/2815 ,  H01L29/04 ,  H01L29/0634 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/417 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/66719 ,  H01L29/66727 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electronic device can include a transistor. In an embodiment, the transistor can include a semiconductor layer having a primary surface and a conductive structure. The conductive structure can include a horizontally-oriented doped region lying adjacent to the primary surface, an underlying doped region spaced apart from the primary surface and the horizontally-oriented doped region, and a vertically-oriented conductive region extending through a majority of the thickness of the semiconductor layer and electrically connecting the doped horizontal region and the underlying doped region. In another embodiment, the transistor can include a gate dielectric layer, wherein the field-effect transistor is designed to have a maximum gate voltage of approximately 20 V, a maximum drain voltage of approximately 30 V, and a figure of merit no greater than approximately 30 mΩ*nC.A process of forming an electronic device can include providing a workpiece comprising a substrate, including an underlying doped region, and a semiconductor layer overlying the underlying doped region, wherein the semiconductor layer has a primary surface spaced apart from the underlying doped region. The process can also include forming a vertically-oriented conductive region extending from the primary surface to the underlying doped region, and forming a horizontally-oriented doped region adjacent to the primary surface. In a finished form of the electronic device, the horizontally-oriented doped region extends further in a lateral direction toward a region where a source region has been or will be formed, as compared to the vertically-oriented conductive region. The electronic device includes a transistor that includes the underlying doped region, the vertically-oriented conductive region, and the horizontally-oriented doped region.

摘要翻译： 电子器件可以包括晶体管。 在一个实施例中，晶体管可以包括具有主表面和导电结构的半导体层。 导电结构可以包括位于与主表面相邻的水平取向的掺杂区域，与初级表面和水平取向的掺杂区域间隔开的下面的掺杂区域以及延伸穿过厚度的大部分的垂直取向的导电区域 并且电连接掺杂的水平区域和下面的掺杂区域。 在另一个实施例中，晶体管可以包括栅极电介质层，其中场效应晶体管被设计为具有大约20V的最大栅极电压，大约30V的最大漏极电压和不大于大约的品质因数 30 m＆OHgr; * nC。 形成电子器件的工艺可以包括提供包括衬底的工件，包括下面的掺杂区域和覆盖下面的掺杂区域的半导体层，其中半导体层具有与下面的掺杂区域间隔开的主表面。 该方法还可以包括形成从主表面延伸到下掺杂区的垂直取向的导电区，以及形成与主表面相邻的水平取向的掺杂区。 在电子器件的成品形式中，与垂直取向的导电区域相比，水平取向的掺杂区域在横向方向上进一步朝向已经或将要形成源极区域的区域延伸。 电子器件包括晶体管，其包括下面的掺杂区域，垂直取向的导电区域和水平取向的掺杂区域。

公开(公告)号：US07902017B2

公开(公告)日：2011-03-08

申请号：US12337271

申请日：2008-12-17

申请人： Gary H. Loechelt

发明人： Gary H. Loechelt

IPC分类号： H01L21/00

CPC分类号： H01L29/0878 ,  H01L21/2815 ,  H01L29/0847 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/42376 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/66696 ,  H01L29/7816 ,  H01L29/7835

摘要： A process of forming an electronic device can include providing a workpiece comprising a substrate, including an underlying doped region, and a semiconductor layer overlying the underlying doped region, wherein the semiconductor layer has a primary surface spaced apart from the underlying doped region. The process can also include forming a vertically-oriented conductive region extending from the primary surface to the underlying doped region, and forming a horizontally-oriented doped region adjacent to the primary surface. In a finished form of the electronic device, the horizontally-oriented doped region extends further in a lateral direction toward a region where a source region has been or will be formed, as compared to the vertically-oriented conductive region. The electronic device includes a transistor that includes the underlying doped region, the vertically-oriented conductive region, and the horizontally-oriented doped region.

摘要翻译： 形成电子器件的工艺可以包括提供包括衬底的工件，包括下面的掺杂区域和覆盖下面的掺杂区域的半导体层，其中半导体层具有与下面的掺杂区域间隔开的主表面。 该方法还可以包括形成从主表面延伸到下掺杂区的垂直取向的导电区，以及形成与主表面相邻的水平取向的掺杂区。 在电子器件的成品形式中，与垂直取向的导电区域相比，水平取向的掺杂区域在横向方向上进一步朝向已经或将要形成源极区域的区域延伸。 电子器件包括晶体管，其包括下面的掺杂区域，垂直取向的导电区域和水平取向的掺杂区域。

公开(公告)号：US07821063B2

公开(公告)日：2010-10-26

申请号：US12131295

申请日：2008-06-02

申请人： Gary H. Loechelt ,  Robert B. Davies ,  David H. Lutz

发明人： Gary H. Loechelt ,  Robert B. Davies ,  David H. Lutz

IPC分类号： H01L29/76

CPC分类号： H01L29/7802 ,  H01L21/26586 ,  H01L21/2815 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66719 ,  H01L29/66727

摘要： In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a localized region of doping near a portion of a channel region where current exits during operation.

摘要翻译： 在一个实施例中，半导体器件形成在半导体材料体中。 半导体器件包括在操作期间电流离开的沟道区域的一部分附近的局部化掺杂区域。

公开(公告)号：US07276747B2

公开(公告)日：2007-10-02

申请号：US11112570

申请日：2005-04-25

申请人： Gary H. Loechelt ,  Peter J. Zdebel

发明人： Gary H. Loechelt ,  Peter J. Zdebel

IPC分类号： H01L29/76

CPC分类号： H01L29/7802 ,  H01L21/2815 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/66719 ,  H01L29/66727

摘要： In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a screening electrode spaced apart from a channel region.

摘要翻译： 在一个实施例中，半导体器件形成在半导体材料体中。 半导体器件包括与沟道区间隔开的屏蔽电极。

公开(公告)号：US06809396B2

公开(公告)日：2004-10-26

申请号：US10303168

申请日：2002-11-25

申请人： Peter J. Zdebel ,  Misbahul Azam ,  Gary H. Loechelt ,  James R. Morgan ,  Julio C. Costa

发明人： Peter J. Zdebel ,  Misbahul Azam ,  Gary H. Loechelt ,  James R. Morgan ,  Julio C. Costa

IPC分类号： H01L2973

CPC分类号： H01L21/82285 ,  H01L27/0826

摘要： An integrated circuit (100) includes high performance complementary bipolar NPN and PNP vertical transistors (10, 20). The NPN transistor is formed on a semiconductor substrate whose surface (24) is doped to form a PNP base region (28, 70). A film (32, 34, 30) is formed on the surface with an opening (42) over an edge of the base region. A first conductive spacer (48) is formed along a first sidewall (78) of the opening to define a PNP emitter region (67) within the base region. A second conductive spacer (47) is formed along a second sidewall (76) of the opening to define a PNP collector region (66).

摘要翻译： 集成电路（100）包括高性能互补双极NPN和PNP垂直晶体管（10,20）。 NPN晶体管形成在其表面（24）被掺杂以形成PNP基极区域（28,70）的半导体衬底上。 在该表面上形成一个薄膜（32,34,30），该开口（42）位于基部区域的边缘上。 沿着开口的第一侧壁（78）形成第一导电间隔物（48），以在基极区域内限定PNP发射极区域（67）。 第二导电间隔物（47）沿着开口的第二侧壁（76）形成以限定PNP收集区（66）。

公开(公告)号：US08582317B2

公开(公告)日：2013-11-12

申请号：US12787861

申请日：2010-05-26

申请人： Yenting Wen ,  Kisun Lee ,  Michael Stapleton ,  Gary H. Loechelt

发明人： Yenting Wen ,  Kisun Lee ,  Michael Stapleton ,  Gary H. Loechelt

IPC分类号： H05K7/02 ,  H01L21/50 ,  H01L23/48 ,  H01L21/77

CPC分类号： H01L24/97 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49589 ,  H01L23/49593 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06181 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/37124 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/40106 ,  H01L2224/40245 ,  H01L2224/41175 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/83

摘要： A semiconductor component and a method of manufacturing the semiconductor component that reduces parasitic elements. A semiconductor chip is coupled to a semiconductor chip receiving area of a support structure. The semiconductor chip has at least two power semiconductor devices. A drain contact of a first power semiconductor device is coupled to a source contact of a second power semiconductor device and the drain and source contacts of the first and second power semiconductor devices are joined to the semiconductor chip receiving area. Another semiconductor chip may be bonded to a second semiconductor chip receiving area of the support structure. An energy storage element may be coupled between the source contact of the first power semiconductor device and the drain contact of the second semiconductor device. A protective structure may be formed over the semiconductor chips and the energy storage element.

摘要翻译： 半导体元件和减少寄生元件的半导体元件的制造方法。 半导体芯片耦合到支撑结构的半导体芯片接收区域。 半导体芯片具有至少两个功率半导体器件。 第一功率半导体器件的漏极接触耦合到第二功率半导体器件的源极接触，并且第一和第二功率半导体器件的漏极和源极触点接合到半导体芯片接收区域。 另一个半导体芯片可以结合到支撑结构的第二半导体芯片接收区域。 能量存储元件可以耦合在第一功率半导体器件的源极触点和第二半导体器件的漏极触点之间。 可以在半导体芯片和能量存储元件上形成保护结构。

公开(公告)号：US08530299B2

公开(公告)日：2013-09-10

申请号：US13353223

申请日：2012-01-18

申请人： Gary H. Loechelt ,  Gordon M. Grivna

发明人： Gary H. Loechelt ,  Gordon M. Grivna

IPC分类号： H01L21/8238

CPC分类号： H01L21/823892 ,  H01L21/2815 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/66696 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electronic device including an integrated circuit can include a buried conductive region and a semiconductor layer overlying the buried conductive region, and a vertical conductive structure extending through the semiconductor layer and electrically connected to the buried conductive region. The integrated circuit can further include a doped structure having an opposite conductivity type as compared to the buried conductive region, lying closer to an opposing surface than to a primary surface of the semiconductor layer, and being electrically connected to the buried conductive region. The integrated circuit can also include a well region that includes a portion of the semiconductor layer, wherein the portion overlies the doped structure and has a lower dopant concentration as compared to the doped structure. In other embodiment, the doped structure can be spaced apart from the buried conductive region.

摘要翻译： 包括集成电路的电子设备可以包括掩埋导电区域和覆盖掩埋导电区域的半导体层，以及延伸穿过半导体层并电连接到掩埋导电区域的垂直导电结构。 集成电路还可以包括与掩埋导电区相比具有相对导电类型的掺杂结构，其比与半导体层的主表面更接近于相对表面，并且电连接到掩埋导电区。 集成电路还可以包括包括半导体层的一部分的阱区，其中该部分覆盖掺杂结构并且与掺杂结构相比具有较低的掺杂剂浓度。 在另一个实施例中，掺杂结构可以与掩埋的导电区域间隔开。