公开(公告)号：US20140040552A1

公开(公告)日：2014-02-06

申请号：US13958399

申请日：2013-08-02

Applicant: QUALCOMM Incorporated

Inventor： Bohuslav Rychlik ,  Tzung Ren Tzeng ,  Andrew Evan Gruber ,  Alexei V. Bourd ,  Colin Christopher Sharp ,  Eric Demers

IPC: G06F12/08

CPC classification number: G06F12/0815 ,  G06F12/0811 ,  G06F12/0833 ,  G06F12/0837 ,  G06F12/0891 ,  G06F2212/302

Abstract: A method includes storing, with a first programmable processor, shared variable data to cache lines of a first cache of the first processor. The method further includes executing, with the first programmable processor, a store-with-release operation, executing, with a second programmable processor, a load-with-acquire operation, and loading, with the second programmable processor, the value of the shared variable data from a cache of the second programmable processor.

Abstract translation: 一种方法包括使用第一可编程处理器将共享变量数据存储到第一处理器的第一高速缓存的高速缓存行。 该方法还包括利用第一可编程处理器执行存储释放操作，利用第二可编程处理器执行带有采集操作的负载，并且与第二可编程处理器一起执行共享的值 来自第二可编程处理器的缓存的可变数据。

公开(公告)号：US09015400B2

公开(公告)日：2015-04-21

申请号：US13785877

申请日：2013-03-05

Applicant: QUALCOMM Incorporated

Inventor： Thomas Zeng ,  Azzedine Touzni ,  Tzung Ren Tzeng ,  Phil J. Bostley

IPC: G06F12/02 ,  G06F12/10 ,  G06F9/455

CPC classification number: G06F12/1027 ,  G06F9/45533 ,  G06F9/45545 ,  G06F9/45558 ,  G06F12/10 ,  G06F2212/151 ,  G06F2212/171 ,  G06F2212/507 ,  G06F2212/654 ,  G06F2212/684

Abstract: A computer system and a method are provided that reduce the amount of time and computing resources that are required to perform a hardware table walk (HWTW) in the event that a translation lookaside buffer (TLB) miss occurs. If a TLB miss occurs when performing a stage 2 (S2) HWTW to find the PA at which a stage 1 (S1) page table is stored, the MMU uses the IPA to predict the corresponding PA, thereby avoiding the need to perform any of the S2 table lookups. This greatly reduces the number of lookups that need to be performed when performing these types of HWTW read transactions, which greatly reduces processing overhead and performance penalties associated with performing these types of transactions.

Abstract translation: 提供一种计算机系统和方法，其在发生翻译后备缓冲器（TLB）未命中的情况下减少执行硬件表行走（HWTW）所需的时间量和计算资源。 如果执行阶段2（S2）HWTW以找到存储第1（S1）页表的PA时发生TLB未命中，则MMU使用IPA来预测对应的PA，从而避免执行任何 S2表查找。 这大大减少了执行这些类型的HWTW读取事务时需要执行的查找次数，这大大降低了与执行这些类型的事务相关联的处理开销和性能损失。

公开(公告)号：US20160019168A1

公开(公告)日：2016-01-21

申请号：US14510804

申请日：2014-10-09

Applicant: QUALCOMM Incorporated

Inventor： Bohuslav Rychlik ,  Jason Edward Podaima ,  Andrew Evan Gruber ,  Tzung Ren Tzeng ,  Zhenbiao Ma

IPC: G06F12/14 ,  G06F3/06

CPC classification number: G06F12/1483 ,  G06F3/0622 ,  G06F3/0637 ,  G06F3/067 ,  G06F12/1009 ,  G06F2212/152

Abstract: The aspects include systems and methods of managing virtual memory page shareability. A processor or memory management unit may set in a page table an indication that a virtual memory page is not shareable with an outer domain processor. The processor or memory management unit may monitor for when the outer domain processor attempts or has attempted to access the virtual memory page. In response to the outer domain processor attempting to access the virtual memory page, the processor may perform a virtual memory page operation on the virtual memory page.

Abstract translation: 这些方面包括管理虚拟内存页面共享性的系统和方法。 处理器或存储器管理单元可以在页表中设置虚拟存储器页不能与外域处理器共享的指示。 处理器或存储器管理单元可以监视外部域处理器何时尝试或尝试访问虚拟存储器页面。 响应于外部域处理器尝试访问虚拟存储器页面，处理器可以在虚拟存储器页面上执行虚拟存储器页面操作。

公开(公告)号：US09218289B2

公开(公告)日：2015-12-22

申请号：US13958399

申请日：2013-08-02

Applicant: QUALCOMM Incorporated

Inventor： Bohuslav Rychlik ,  Tzung Ren Tzeng ,  Andrew Evan Gruber ,  Alexei V. Bourd ,  Colin Christopher Sharp ,  Eric Demers

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/0815 ,  G06F12/0811 ,  G06F12/0833 ,  G06F12/0837 ,  G06F12/0891 ,  G06F2212/302

Abstract: A method includes storing, with a first programmable processor, shared variable data to cache lines of a first cache of the first processor. The method further includes executing, with the first programmable processor, a store-with-release operation, executing, with a second programmable processor, a load-with-acquire operation, and loading, with the second programmable processor, the value of the shared variable data from a cache of the second programmable processor.

Abstract translation: 一种方法包括使用第一可编程处理器将共享变量数据存储到第一处理器的第一高速缓存的高速缓存行。 该方法还包括利用第一可编程处理器执行存储释放操作，利用第二可编程处理器执行带有采集操作的负载，并且与第二可编程处理器一起执行共享的值 来自第二可编程处理器的缓存的可变数据。

公开(公告)号：US09330026B2

公开(公告)日：2016-05-03

申请号：US13785979

申请日：2013-03-05

Applicant: QUALCOMM Incorporated

Inventor： Thomas Zeng ,  Azzedine Touzni ,  Tzung Ren Tzeng ,  Phil J. Bostley

IPC: G06F12/14 ,  G06F12/1027 ,  G06F21/79 ,  G06F12/10

CPC classification number: G06F12/145 ,  G06F9/45504 ,  G06F12/1027 ,  G06F12/1491 ,  G06F21/79 ,  G06F2212/1032 ,  G06F2212/151 ,  G06F2212/152 ,  G06F2212/654 ,  G06F2212/68

Abstract: A security apparatus and method are provided for performing a security algorithm that prevents unauthorized access to contents of a physical address (PA) that have been loaded into a storage element of the computer system as a result of performing a prediction algorithm during a hardware table walk that uses a predictor to predict a PA based on a virtual address (VA). When the predictor is enabled, it might be possible for a person with knowledge of the system to configure the predictor to cause contents stored at a PA of a secure portion of the main memory to be loaded into a register in the TLB. In this way, a person who should not have access to contents stored in secure portions of the main memory could indirectly gain unauthorized access to those contents. The apparatus and method prevent such unauthorized access to the contents by masking the contents under certain conditions.

Abstract translation: 提供了一种安全装置和方法，用于执行安全算法，该安全算法防止在硬件表步行期间执行预测算法的结果，防止对已经加载到计算机系统的存储元件中的物理地址（PA）的内容的未经授权的访问 其使用预测器来基于虚拟地址（VA）预测PA。 当启用预测器时，具有系统知识的人可能配置预测器以使存储在主存储器的安全部分的PA的内容被加载到TLB中的寄存器中。 以这种方式，不能访问存储在主存储器的安全部分中的内容的人可以间接地获得对这些内容的未经授权的访问。 该装置和方法通过在某些条件下屏蔽内容来防止对该内容的未经授权的访问。

公开(公告)号：US20140258663A1

公开(公告)日：2014-09-11

申请号：US13785979

申请日：2013-03-05

Applicant: QUALCOMM INCORPORATED

Inventor： Thomas Zeng ,  Azzedine Touzni ,  Tzung Ren Tzeng ,  Phil J. Bostley

IPC: G06F12/14

CPC classification number: G06F12/145 ,  G06F9/45504 ,  G06F12/1027 ,  G06F12/1491 ,  G06F21/79 ,  G06F2212/1032 ,  G06F2212/151 ,  G06F2212/152 ,  G06F2212/654 ,  G06F2212/68

Abstract: A security apparatus and method are provided for performing a security algorithm that prevents unauthorized access to contents of a physical address (PA) that have been loaded into a storage element of the computer system as a result of performing a prediction algorithm during a hardware table walk that uses a predictor to predict a PA based on a virtual address (VA). When the predictor is enabled, it might be possible for a person with knowledge of the system to configure the predictor to cause contents stored at a PA of a secure portion of the main memory to be loaded into a register in the TLB. In this way, a person who should not have access to contents stored in secure portions of the main memory could indirectly gain unauthorized access to those contents. The apparatus and method prevent such unauthorized access to the contents by masking the contents under certain conditions.

Abstract translation: 提供一种安全装置和方法，用于执行安全算法，以防止在硬件表步行期间执行预测算法的结果，防止对已经加载到计算机系统的存储元件中的物理地址（PA）的内容的未经授权的访问 其使用预测器来基于虚拟地址（VA）预测PA。 当启用预测器时，具有系统知识的人可能配置预测器以使存储在主存储器的安全部分的PA的内容被加载到TLB中的寄存器中。 以这种方式，不能访问存储在主存储器的安全部分中的内容的人可以间接地获得对这些内容的未经授权的访问。 该装置和方法通过在某些条件下屏蔽内容来防止对该内容的未经授权的访问。

公开(公告)号：US20140258586A1

公开(公告)日：2014-09-11

申请号：US13785877

申请日：2013-03-05

Applicant: QUALCOMM INCORPORATED

Inventor： Thomas Zeng ,  Azzedine Touzni ,  Tzung Ren Tzeng ,  Phil J. Bostley

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F9/45533 ,  G06F9/45545 ,  G06F9/45558 ,  G06F12/10 ,  G06F2212/151 ,  G06F2212/171 ,  G06F2212/507 ,  G06F2212/654 ,  G06F2212/684

Abstract: A computer system and a method are provided that reduce the amount of time and computing resources that are required to perform a hardware table walk (HWTW) in the event that a translation lookaside buffer (TLB) miss occurs. If a TLB miss occurs when performing a stage 2 (S2) HWTW to find the PA at which a stage 1 (S1) page table is stored, the MMU uses the IPA to predict the corresponding PA, thereby avoiding the need to perform any of the S2 table lookups. This greatly reduces the number of lookups that need to be performed when performing these types of HWTW read transactions, which greatly reduces processing overhead and performance penalties associated with performing these types of transactions.

Abstract translation: 提供一种计算机系统和方法，其在发生翻译后备缓冲器（TLB）未命中的情况下减少执行硬件表行走（HWTW）所需的时间量和计算资源。 如果执行阶段2（S2）HWTW以找到存储第1（S1）页表的PA时发生TLB未命中，则MMU使用IPA预测相应的PA，从而避免执行任何 S2表查找。 这大大减少了执行这些类型的HWTW读取事务时需要执行的查找次数，这大大降低了与执行这些类型的事务相关联的处理开销和性能损失。